Impedance matching circuit for matching planar antennas
View Patent ↗A circuit includes a signal path having a node between a signal path input and a signal path output. A first inductive element is connected between the signal path input and the node and a first capacitive element whose capacitance is variably adjustable is connected between the node and the signal path output. A second variable-capacitance capacitive element is connected between the signal path input and ground. A second inductive element is connected between the node and ground, and a third inductive element is connected between the signal path output and ground.
1. An impedance matching circuit for matching planar antennas, comprising:
a signal path having a node between a signal path input and a signal path output;
a first inductive element coupled between the signal path input and the node;
a first variable-capacitance capacitive element coupled between the node and the signal path output;
a second variable-capacitance capacitive element coupled between the signal path input and a ground;
a second inductive element coupled between the node and ground; and
a third inductive element coupled between the signal path output and ground.
2. The impedance matching circuit according to claim 1 , wherein the first, second and third inductive elements have Q factors of greater than 15 and wherein the first and second variable-capacitance capacitive elements have Q factors of greater than 10.
3. The impedance matching circuit according to claim 1 , wherein the first inductive element has an inductance of between 0.5 and 22 nH, wherein the second inductive element has an inductance of between 0.5 and 22 nH, and wherein the third inductive element has an inductance of between 0.5 and 22 nH, and wherein the first capacitive element and the second capacitive element each have a capacitance that can be adjusted between 0.5 and 12 pF.
4. The impedance matching circuit according to claim 1 , wherein a tuning ratio of one of the variable-capacitance capacitive elements is between 3.5:1 and 4.5:1.
5. The impedance matching circuit according to claim 1 , wherein a tuning ratio of one of the variable-capacitance capacitive elements is between 4.5:1 and 5.5:1.
6. The impedance matching circuit according to claim 1 , wherein a tuning ratio of one of the variable-capacitance capacitive elements is between 5.5:1 and 6.5:1.
7. The impedance matching circuit according to claim 1 , wherein the first and/or the second variable-capacitance element comprises a variable-capacitance capacitive element selected from the group co of a varactor diode with a dielectric layer comprising barium strontium titanate, a varactor diode with a dielectric layer comprising bismuth zinc niobate, a capacitive element produced using CMOS technology, a connection of MEMS capacitors and a semiconductor varactor diode.
8. The impedance matching circuit according to claim 1 , further comprising a fifth capacitive element coupled between the node and the signal path output in parallel with the first capacitive element.
9. The impedance matching circuit according to claim 1 , further comprising a directional coupler coupled to the signal path input.
10. The impedance matching circuit according to claim 1 , further comprising a front-end module coupled to the signal path input.
11. The impedance matching circuit according to claim 1 , further comprising a duplexer coupled to the signal path.
12. The impedance matching circuit according to claim 1 , wherein the first, second and third inductive elements are in the form of metallizations in a multilayer substrate selected from HTCC, LTCC, FR4 and laminate.
13. The impedance matching circuit according to claim 1 , further comprising a third capacitive element having a Q factor of greater than 50 and a capacitance of between 1 and 35 pF and a fourth inductive element having a Q factor of greater than 15 and an inductance of between 0.5 and 10 nH, wherein the third capacitive element and the fourth inductive element are coupled in series between the signal path input and ground.
14. The impedance matching circuit according to claim 13 , further comprising a fourth capacitive element which has a Q factor of greater than 50 and a capacitance of between 4 and 18 pF and is coupled between the signal path input and ground.
15. The impedance matching circuit according to claim 14 , wherein the Q factor of the fourth capacitive element is greater than a Q factor of the second variable-capacitance capacitive element.
16. The impedance matching circuit according to claim 1 , wherein a tuning ratio of one of the variable-capacitance capacitive elements is between 2.5:1 and 3.5:1.
17. The impedance matching circuit according to claim 16 , wherein the tuning ratio of one of the variable-capacitance capacitive elements is 3:1.
18. The impedance matching circuit according to claim 1 , wherein the impedance matching circuit is configured for use in a mobile communication device having a transmitting path, a receiving path and a PILA-type planar antenna, wherein
the signal path input is coupled to the transmitting path and to the receiving path, and
wherein the signal path output is coupled to the planar antenna via an antenna lead having an impedance of between 10 ohms and 60 ohms.
19. The impedance matching circuit according to claim 18 , wherein the impedance matching circuit is configured to match the transmitting path in a transmitting frequency band and the receiving path in a receiving frequency band to the planar antenna with a standing wave ratio in the transmitting path of less than 3.
20. The impedance matching circuit according to claim 18 , wherein the impedance matching circuit is configured to match the transmitting path in a transmitting frequency band and the receiving path in a receiving frequency band to the planar antenna with a standing wave ratio in the receiving path of less than 4.
21. The impedance matching circuit according to claim 18 , wherein the impedance matching circuit is configured for use in CDMA, W-CDMA or GSM frequency bands between 500 and 4500 MHz.
22. The impedance matching circuit according to claim 18 , wherein the impedance matching circuit is configured for use in DVB-H, W-LAN or WIFI frequency bands between 500 and 4500 MHz.
23. The impedance matching circuit according to claim 18 , further comprising an antenna lead coupled between the signal path output and the planar antenna, the antenna lead having an impedance of between 10 and 60 ohms.
24. An impedance matching circuit for matching planar antennas, comprising
a signal path having a node between a signal path input and a signal path output;
a first inductive element coupled between the signal path input and the node;
a first variable-capacitance capacitive element coupled between the node and the signal path output;
a second variable-capacitance capacitive element coupled between the signal path input and a ground node;
a second inductive element coupled between the node and the ground node;
a third inductive element coupled between the signal path output and the ground node;
a third capacitive element;
a fourth inductive element, wherein the third capacitive element and the fourth inductive element are coupled in series between the signal path input and the ground node;
a fourth capacitive element coupled between the signal path input and the ground node; and
a fifth capacitive element coupled between the node and the signal path output in parallel with the first capacitive element.
25. The impedance matching circuit according to claim 24 , further comprises a directional coupler coupled to the signal path input and a front-end module coupled to the signal path input.