P-type field-effect transistor and method of production
View Patent ↗An n-layer is arranged above a substrate, which can be GaAs, and a p-layer ( 4 ) is arranged on the n-layer. The p-layer is separated by a gate electrode into two separate portions forming source and drain. The gate electrode is insulated from the semiconductor material by a gate dielectric. Source/drain contacts are electrically conductively connected with the portions of the p-layer.
1. A p-type field-effect transistor, comprising:
a substrate of GaAs;
an n + -layer;
an n-layer arranged on the n + -layer, the n-layer having a surface, the n-layer being located above the substrate;
a p-layer having two separate portions arranged on the surface of the n-layer;
a gate electrode between the portions of the p-layer;
a gate dielectric located between the gate electrode and the n-layer and between the gate electrode and each portion of the p-layer;
a first source/drain contact electrically conductively connected to one of the portions of the p-layer; and
a second source/drain contact electrically conductively connected to the other of the portions of the p-layer.
2. The field-effect transistor according to claim 1 , further comprising a bulk contact electrically conductively connected to the n + -layer.
3. The field-effect transistor according to claim 1 , wherein the n-layer and the p-layer form a mesa.
4. The field-effect transistor according to claim 1 , further comprising a first source/drain contact layer between the first source/drain contact and the p-layer and a second source/drain contact layer between the second source/drain contact and the p-layer.
5. A semiconductor device comprising:
the p-type field-effect transistor according the claim 1 ; and
a vertical npn heterojunction bipolar transistor disposed at a second region of the GaAs substrate and laterally spaced from the field effect transistor, the heterojunction bipolar transistor comprising:
a collector located in the first n-layer;
a base located in the p-layer over the collector; and
an emitter located in the second n-layer over the base.
6. The device according to claim 5 , wherein the heterojunction bipolar transistor further comprises a subcollector located in the n+ layer.
7. The device according to claim 5 , further comprising a first source/drain contact electrically conductively connected to first source/drain the first portion of the p-layer and a second source/drain contact electrically conductively connected to second source/drain the second portion of the p-layer.
8. The device according to claim 7 , further comprising a first source/drain contact layer arranged between the first source/drain contact and the first portion of the p-layer and a second source/drain contact layer arranged between the second source/drain contact and the second portion of the p-layer.
9. The device according to claim 5 , further comprising a bulk contact electrically conductively connected to the n + -layer.
10. The device according to claim 5 , wherein the first n-layer, the player and the second n-layer form a mesa.
11. The device according to claim 5 , wherein the gate electrode is formed in a recess between the first portion of the p-layer and the second portion of the p-layer.
12. The device according to claim 5 , wherein the gate dielectric comprises silicon nitride.
13. A method for forming a field-effect transistor, the method comprising:
forming a layer sequence above a surface of a substrate of GaAs provided with an n + -layer; the layer sequence comprising an n-layer on the n + -layer and a p-layer on the n-layer;
forming a recess in the p-layer such that the p-layer is divided into two separate portions,
forming a gate dielectric in the recess,
forming a gate electrode over the gate dielectric;
applying source/drain contacts to each of the portions of the p-layer; and
applying a bulk contact to the n + -layer.
14. The method according to claim 13 , wherein the gate dielectric comprises silicon nitride.
15. A method for forming a field-effect transistor, the method comprising:
forming a layer sequence above a surface of a substrate of GaAs provided with an n + -layer; the layer sequence comprising an n-layer on the n + -layer and a p-layer on the n-layer;
forming a recess in the p-layer such that the p-layer is divided into two separate portions,
forming a gate dielectric in the recess,
forming a gate electrode over the gate dielectric;
applying source/drain contacts to each of the portions of the p-layer;
wherein forming the layer sequence comprises performing a manufacturing process of an npn HBT to form the n-layer, the p-layer and a further n-layer that is applied on the p-layer and to structure the layers to form the field-effect transistor and an npn bipolar transistor, wherein a subcollector of the npn bipolar transistor is formed in the n + -layer.
16. The method according to claim 15 , wherein the gate dielectric comprises silicon nitride.