IP Library Granted Patent US 8,389,972
Granted Patent B2
US 8,389,972 · App. 13/129,215 · Granted Mar 5, 2013

Nonvolatile memory device and method of manufacturing the same

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Quick Facts
Patent No.
US 8,389,972
App. No.
13/129,215
Granted
Mar 5, 2013
Kind
B2
Abstract

To realize miniaturization and increased capacity of memories by lowering break voltage for causing resistance change and suppressing variation in break voltage. The nonvolatile memory device ( 10 ) in the present invention includes: a lower electrode ( 105 ) formed above a substrate ( 100 ); a first variable resistance layer ( 106 a ) formed above the lower electrode ( 105 ) and comprising a transitional metal oxide; a second variable resistance layer ( 106 b ) formed above the first variable resistance layer ( 106 a ) and comprising a transitional metal oxide having higher oxygen content than the transitional metal oxide of the first variable resistance layer ( 106 a ); and an upper electrode ( 107 ) formed above the second variable resistance layer ( 106 b ), wherein a step ( 106 ax ) is formed in an interface between the first variable is resistance layer ( 106 a ) and the second variable resistance layer ( 106 b ). The second variable resistance layer ( 106 b ) is formed covering the step ( 106 ax ) and has a bend ( 106 bx ) above the step ( 106 ax ).

Claims (33)

1. A nonvolatile memory device comprising:

a substrate;

a lower electrode formed above said substrate;

a first variable resistance layer formed above said lower electrode and comprising a first transitional metal oxide;

a second variable resistance layer formed above said first variable resistance layer and comprising a second transitional metal oxide having an oxygen content that is higher than an oxygen content of the first transitional metal oxide; and

an upper electrode formed above said second variable resistance layer,

wherein a step is formed in an interface between said first variable resistance layer and said second variable resistance layer, and

said second variable resistance layer is formed covering the step and has a bend above the step.

2. The nonvolatile memory device according to claim 1 , further comprising

a contact plug below said lower electrode,

wherein an interface between said lower electrode and said first variable resistance layer is flat.

3. The nonvolatile memory device according to claim 1 ,

wherein the bend of said second variable resistance layer is straight-shaped when said second variable resistance layer is seen from above.

4. The nonvolatile memory device according to claim 1 ,

wherein the bend of said second variable resistance layer is ring-shaped when said second variable resistance layer is seen from above.

5. The nonvolatile memory device according to claim 1 ,

wherein the step includes plural steps, and there is a crossing point at which the plural steps cross each other.

6. The nonvolatile memory device according to claim 1 ,

wherein the first transitional metal oxide and the second transitional metal oxide each comprise an oxide of tantalum, hafnium, or zirconium.

7. The nonvolatile memory device according to claim 1 ,

wherein a diode element is formed in contact with said lower electrode or said upper electrode.

8. A method of manufacturing a nonvolatile memory device, said method comprising:

forming a lower electrode above a substrate;

forming a first variable resistance layer above the lower electrode, the first variable resistance layer comprising a first transitional metal oxide;

forming a step in a surface of the first variable resistance layer;

forming a second variable resistance layer to cover the step of the first variable resistance layer and have a bend above the step, the second variable resistance layer comprising a second transitional metal oxide having an oxygen content that is higher than an oxygen content of the first transitional metal oxide; and

forming an upper electrode above the second variable resistance layer.

9. A method of manufacturing a nonvolatile memory device, said method comprising:

forming a lower electrode above a substrate;

forming a first variable resistance layer above the lower electrode, the first variable resistance layer comprising a first transitional metal oxide;

forming a second variable resistance layer above the first variable resistance layer, the second variable resistance layer comprising a second transitional metal oxide having an oxygen content that is higher than an oxygen content of the first transitional metal oxide;

additionally stacking the second variable resistance layer after forming a step in the second variable resistance layer, so as to cover the step; and

forming an upper electrode above the additionally-stacked second variable resistance layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2011
From: MIKAWA, TAKUMI; KAWASHIMA, YOSHIO
To: PANASONIC CORPORATION
Reel/Frame 026581/0233 →