RF CMOS transistor design
View Patent ↗An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line. In an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers.
1. A transistor for RF operation fabricated in a MOS process, the transistor comprising:
an active area;
a plurality of gate fingers;
a plurality of local interconnect lines constrained substantially to above the active area of the transistor;
a source terminal and a drain terminal arranged orthogonally to each of the plurality of local interconnect lines, wherein each terminal is electrically connected to at least one local interconnect line wherein the source terminal and the drain terminal are substantially wider than a local interconnect line and the source terminal and the drain terminal are routed above the active region, including above the gate fingers;
a dummy gate electrode structure; and
a well-tap adjacent to the dummy gate electrode structure,
and wherein the dummy gate electrode structure is electrically connected to the well-tap.
2. A transistor according to claim 1 , wherein the source terminal and the drain terminal are formed in different metal layers.
3. A transistor according to claim 1 , further comprising a second drain terminal and wherein the drain terminals are arranged either side of the source terminal.
4. A transistor according to claim 1 , further comprising a gate strap, and wherein the gate strap is routed substantially across the center of the transistor.
5. A transistor design according to claim 1 , wherein a local interconnect line comprises at least one narrow portion adjacent to a wider portion, and wherein only the at least one narrow portion is connected directly to one of a source terminal and a drain terminal by means of at least one via.
6. A transistor design according to claim 1 , further comprising a well-tie sharing said active area of the transistor.
7. An RF transistor design suitable for fabrication in a MOS process, the transistor design comprising:
a plurality of gate fingers;
a plurality of local interconnect lines constrained substantially to above an active area of the transistor;
a source terminal and a drain terminal arranged orthogonally to each of the plurality of local interconnect lines, wherein each terminal is electrically connected to at least one local interconnect line;
a dummy gate electrode structure; and
a well-tap adjacent to the dummy gate electrode structure,
wherein the source terminal and the drain terminal are substantially wider than a local interconnect line and the source terminal and the drain terminal are routed above the active region, including above the gate fingers;
and wherein the dummy gate electrode structure is electrically connected to the well-tap.
8. A transistor design according to claim 7 , wherein the source terminal and the drain terminal are formed in different metal layers.
9. A transistor design according to claim 7 , further comprising a second drain terminal and wherein the drain terminals are arranged either side of the source terminal.
10. A transistor design according to claim 7 , further comprising a gate strap, and wherein the gate strap is routed substantially across the center of the transistor.
11. A transistor design according to claim 7 , further comprising a well-tie sharing said active area of the transistor.
12. A method of fabricating a transistor for RF operation comprising:
forming an active area on a wafer;
forming a plurality of gate fingers;
forming a plurality of local interconnect lines constrained substantially above the active area in at least a first metal layer; and
forming a source terminal and a drain terminal in at least one subsequent metal layer, wherein the source terminal and the drain terminal arranged orthogonally to each of the plurality of local interconnect lines and are substantially wider than a local interconnect line and the source terminal and the drain terminal are routed above the active area, including above the gate fingers and each terminal is electrically connected to at least one local interconnect line;
forming a dummy gate electrode structure; and
forming a well-tap adjacent to the dummy gate electrode structure, wherein the dummy gate electrode structure is electrically connected to the well-tap.
13. A method according to claim 12 , wherein forming a source terminal and a drain terminal in at least one subsequent metal layer comprises:
forming the source terminal in at least a second metal layer; and
forming the drain terminal in at least a third metal layer.
14. A method according to claim 12 , wherein forming a source terminal and a drain terminal in at least one subsequent metal layer comprises:
forming the drain terminal in at least a second metal layer; and
forming the source terminal in at least a third metal layer.
15. A method according to claim 12 further comprising:
forming a gate strap in at least a fourth metal layer, and wherein the gate strap is routed substantially across the centre of the transistor.
16. A method according to claim 15 , wherein:
said at least a first metal layer comprises a metal- 1 layer and a metal- 2 layer;
said at least a second metal layer comprises a metal- 3 layer;
said at least a third metal layer comprises a metal- 4 layer and a metal- 5 layer; and
said at least a fourth metal layer comprises a metal- 6 layer.