HFET with low access resistance
A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a Hetero-structure FET structure, where the access regions have been eliminated so as to effectively obtain a lower specific on-resistance, and a higher control on the transport properties of the device, drastically reducing the dispersion phenomena associated with these regions. The present invention can be realized both with polar and non-polar (or semi-polar) materials, without requiring delta doping implantation. It can be fabricated as an enhancement or depletion mode device with much higher control on the device threshold voltage with respect to state-of-the-art HFET devices, and achieving superior RF switching performance. Furthermore, due to the absence of access regions, enhancement mode devices can be realized without discontinuity in the channel conductivity, which results in an even lower on-resistance.
1 . A semiconductor hetero-structure field effect transistor comprising:
a semiconductor layer;
at least one semiconductor barrier layer formed above at least a portion of said semiconductor layer;
at least one gate region formed above at least one of said semiconductor barrier layers, and
a source and a drain region formed in said semiconductor layer,
wherein said source and drain regions are formed self-aligned with at least one of said gate regions.
2 . The semiconductor hetero-structure field effect transistor of claim 1 wherein said semiconductor layer is a carrier transport layer, and
whereby the conductive channel of said semiconductor hetero-structure field effect transistor is formed in said carrier transport layer when said semiconductor hetero-structure field effect transistor is turned on.
3 . The semiconductor hetero-structure field effect transistor of claim 1 further comprising one carrier transport layer;
wherein said semiconductor layer is a second barrier layer;
wherein said second barrier layer is formed above said carrier transport layer;
wherein the conductive channel of said semiconductor hetero-structure field effect transistor is formed in said carrier transport layer when said semiconductor hetero-structure field effect transistor is turned on, and whereby said second barrier layer is made of a semiconductor material with a conductivity type opposite with respect to the conductivity type of said conductive channel.
4 . The semiconductor hetero-structure field effect transistor of claim 1 wherein at least one of said semiconductor barrier layers is self-aligned with at least one of said gate regions.
5 . The semiconductor hetero-structure field effect transistor of claim 1 wherein at least one of said semiconductor barrier layers is replaced with a barrier layer made of insulating material.
6 . The semiconductor hetero-structure field effect transistor of claim 1 further comprising at least one buried barrier layer under the conductive channel of said semiconductor hetero-structure field effect transistor.
7 . The semiconductor hetero-structure field effect transistor of claim 1 further comprising multiple gate regions.
8 . The semiconductor hetero-structure field effect transistor of claim 1 further comprising at least one lightly doped region self-aligned with at least one of said gate regions,
wherein at least one of said source and drain regions is replaced with a highly conductive region self-aligned with at least one of said lightly doped regions.
9 . The semiconductor hetero-structure field effect transistor of claim 1 formed with at least one of the semiconductor materials belonging to the group comprising polar, semi-polar and non-polar III-V compounds semiconductors, polar, semi-polar and non-polar II-VI compounds semiconductors, and semiconductors materials comprising elements of the IV group of the periodic table.
10 . The semiconductor hetero-structure field effect transistor of claim 1 wherein at least one of said source and drain regions is replaced with a highly conductive region self-aligned with at least one of said semiconductor barrier layers.
11 . A method for manufacturing a semiconductor hetero-structure field effect transistor comprising:
forming at least one semiconductor barrier layer above at least a portion of a semiconductor layer;
forming at least one gate region above at least one of said semiconductor barrier layers;
forming a source and a drain region in said semiconductor layer,
wherein said source and drain regions are formed self-aligned with at least one of said gate regions.
12 . The method of claim 11 wherein said semiconductor layer is a carrier transport layer, and
whereby the conductive channel of said semiconductor hetero-structure field effect transistor is formed in said carrier transport layer when said semiconductor hetero-structure field effect transistor is turned on.
13 . The method of claim 11 wherein said semiconductor hetero-structure field effect transistor comprises a carrier transport layer;
wherein said semiconductor layer is a second barrier layer;
wherein said second barrier layer is formed above said carrier transport layer;
wherein the conductive channel of said semiconductor hetero-structure field effect transistor is formed in said carrier transport layer when said semiconductor hetero-structure field effect transistor is turned on, and
whereby said second barrier layer is made of a semiconductor material with a conductivity type opposite with respect to the conductivity type of said conductive channel.
14 . The method of claim 11 wherein at least one of said semiconductor barrier layers is self-aligned with at least one of said gate regions.
15 . The method of claim 11 wherein at least one of said semiconductor barrier layers is replaced with a barrier layer made of insulating material.
16 . The method of claim 11 wherein said semiconductor hetero-structure field effect transistor comprises at least one buried barrier layer under the conductive channel of said semiconductor hetero-structure field effect transistor.
17 . The method of claim 11 wherein said semiconductor hetero-structure field effect transistor comprises at least one lightly doped region self-aligned with at least one of said gate regions, and
wherein at least one of said source and drain regions is replaced with a highly conductive region self-aligned with at least one of said lightly doped regions.
18 . The method of claim 11 wherein at least one of said source and drain regions is replaced with a highly conductive region self-aligned with at least one of said semiconductor barrier layers.
19 . A semiconductor hetero-structure field effect transistor comprising:
a carrier transport layer;
at least one semiconductor barrier layer formed above at least a portion of said carrier transport layer;
at least one gate region formed above at least one of said semiconductor barrier layers;
a source and a drain region formed at least partially in at least one of said semiconductor barrier layers;
wherein the conductive channel of said semiconductor hetero-structure field effect transistor is formed in said carrier transport layer when said semiconductor hetero-structure field effect transistor is turned on, and
whereby at least one of said semiconductor barrier layers is made of a semiconductor material with a conductivity type opposite with respect to the conductivity type of said conductive channel.
20 . The semiconductor hetero-structure field effect transistor of claim 19 further comprising at least one lightly doped region self-aligned with at least one of said gate regions, and
wherein at least one of said source and drain regions is replaced with a highly conductive region self-aligned with at least one of said lightly doped regions.