Organic light emitting diode display device and manufacturing method thereof
View Patent ↗An OLED display includes a first polysilicon layer pattern on a substrate having a first gate electrode, a second gate electrode, and a first capacitor electrode, a gate insulating layer pattern, a second polysilicon layer pattern including a first active layer, a second active layer, and a capacitor polycrystalline dummy layer, a third amorphous silicon layer pattern including first source and drain resistant contact layers on a predetermined region of the first active layer, second source and drain resistant contact layers on a predetermined region of the second active layer, and a capacitor amorphous dummy layer on the capacitor polycrystalline dummy layer, and a data metal layer pattern including first source/drain electrodes, second source/drain electrodes, and a second capacitor electrode.
1. An organic light emitting diode (OLED) display, comprising:
a first polysilicon layer pattern on a substrate, the first polysilicon layer pattern being impurity-doped and including a first gate electrode, a second gate electrode, and a first capacitor electrode;
a gate insulating layer pattern on the first polysilicon layer pattern;
a second polysilicon layer pattern including a first active layer, a second active layer, and a capacitor polycrystalline dummy layer on respective first gate electrode, second gate electrode, and first capacitor electrode;
a third amorphous silicon layer pattern, the third amorphous silicon layer pattern being impurity-doped and including first source and drain resistant contact layers on a predetermined region of the first active layer, second source and drain resistant contact layers on a predetermined region of the second active layer, and a capacitor amorphous dummy layer on the capacitor polycrystalline dummy layer;
a data metal layer pattern including a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, and a second capacitor electrode on respective first source resistant contact layer, first drain resistant contact layer, second source resistant contact layer, second drain resistant contact layer, and capacitor amorphous dummy layer;
an interlayer insulating layer on an upper surface of the data metal layer pattern, the interlayer insulating layer partially exposing the upper surface of the data metal layer pattern;
a connecting metal layer pattern on an upper surface of the interlayer insulating layer, the connecting metal layer pattern including a gate line connected to the first gate electrode, a first connector connecting the second gate electrode and the first drain electrode, a second connector connecting the first source electrode and a data line, a third connector connecting the second source electrode and a common power line, and a fourth connector connecting the second drain electrode and the second capacitor electrode, wherein the first connector, the second connector, the third connector, and the fourth connector are in direct contact with the exposed upper surface of the data metal layer pattern; and
a transparent conductive layer pattern on the interlayer insulating layer and the connecting metal layer pattern,
wherein the first source and drain electrodes with the first gate electrode and the first active layer define a first transistor, the second source and drain electrodes with the second gate electrode and the second active layer define a second transistor, and the first and second capacitor electrodes with the capacitor polycrystalline and amorphous dummy layers define a capacitor.
2. The OLED display of claim 1 , wherein:
the second active layer and the capacitor polycrystalline dummy layer are separate layers spaced apart horizontally from each other on the gate insulating layer pattern, the gate insulating layer pattern extending continuously to overlap the second active layer of the second transistor, the capacitor polycrystalline dummy layer of the capacitor, and a space between the second transistor and the capacitor, and
the gate insulating layer pattern includes a plurality of contact holes partially revealing the first polysilicon layer pattern, the gate insulating layer pattern and the first polysilicon layer pattern completely overlapping each other, with the exception of the contact holes.
3. The OLED display of claim 1 , wherein the third amorphous silicon layer pattern and the data metal layer pattern completely overlap each other, the entire third amorphous silicon layer being in direct contact with the second polysilicon layer pattern.
4. The OLED display of claim 1 , wherein the data metal layer includes at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).
5. The OLED display of claim 1 , wherein the transparent conductive layer pattern includes a pixel electrode on the interlayer insulating layer and connected to the second drain electrode.
6. The OLED display of claim 5 , further comprising an organic emission layer and a common electrode stacked on the pixel electrode.
7. The OLED display of claim 1 , wherein the transparent conductive layer pattern includes at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), and aluminum zinc oxide (AZO).