Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device

1. A controller comprising:

a set of first terminals to be coupled to a device that is under control of the controller; and

a control circuit configured to generate and output onto the set of first terminals:

synchronous mode information comprising a selected one of selection and non-selection modes, the selection mode causing the device to return to the controller a first data signal while activating a first data strobe signal that is synchronous in phase with a system clock, the non-selection mode causing the device to return to the controller a second data signal while activating a second data strobe signal that is asynchronous in phase with the system clock signal, and

edge specifying information comprising a selected one of first and second states, the first state causing the device to activate the first data strobe signal at a first timing, the second state causing the device to activate the second data strobe signal at a second timing that is different from the first timing.

2. The controller as claimed in claim 1 , further comprising second and third terminals to be coupled to the device, the second terminal receiving the first data signal in the selection mode and the second data signal in the non-selection mode, the third terminal receiving the first data strobe signal in the second mode and the second data strobe signal in the non-selection mode, the controller being configured to fetch the first data signal in response to the first data strobe signal in the selection mode and the second data signal in response to the second data strobe signal in the non-selection mode.

3. The controller as claimed in claim 2 , further comprising a fourth terminal to be coupled to the device, the control circuit being configured to generate and output the system clock signal onto the fourth terminal.

4. A controller for a memory device, comprising a control circuit that is configured to:

set synchronous mode information into the memory device, the synchronous selection mode information comprising a selected one of selection and non-selection modes,

set edge specifying information into the memory device, the edge specifying information comprising a selected one of first and second states,

set latency information into the memory device, and

issue a data read commend to the memory device, the data read command causing the memory device

to return, after a first period responsive to the latency information has been elapsed, to the controller a first data strobe signal with a first data signal when the selection mode is set,

to return, after a second period of time responsive to the latency information and the first state has been elapsed, to the controller a second data strobe signal with a second data signal when the non-selection mode and the first state are set, and

to return, after a third period of time responsive to the latency information and the second state has been elapsed, to the controller a third data strobe signal with a third data signal when the non-selection mode and the second state are set,

the first data strobe signal being synchronous in phase with a system clock signal, each of the second and third data strobe signals being asynchronous in phase with the system clock signal, and the second and third periods of time being different from each other.

5. The controller as claimed in claim 4 , wherein the second data strobe signal is fixed temporarily at a first logic level at a first timing and then changed between the first logic level and a second logic level, and the third data strobe signal is fixed temporarily at the first logic level at a second timing and then changed between the first logic level and the second logic level, the first and second timings being different from each other.

6. The controller as claimed in claim 5 , wherein the first period of time is different from each of the second and third periods of time.

7. The controller as claimed in claim 6 , wherein the first data strobe signal is fixed temporarily at the first logic level at a third timing and then changed between the first logic level and the second logic level, the third timing being different from each of the first and second timings.

8. The controller as claimed in claim 5 , wherein the control circuit is configured to supply the system clock signal to the memory device.

9. The controller as claimed in claim 8 , further comprising a set of command/address terminals, at least one data terminal and at least one of the data strobe terminal which are coupled to the control circuit, the set of address/command terminals serving to transfer the synchronous selection mode information, the edge specifying information, the latency information and the data read commend to the memory device, the data terminal serving to receive the first, second and third data signals, and the data strobe signal serving to receive the first, second and third data strobe signals.

10. A method comprising:

producing synchronous mode information, the synchronous mode information taking a selection mode when synchronization in phase between a strobe signal and a system clock signal is activated and a non-selection mode when synchronization in phase between the strobe signal and the system clock signal is deactivated; and

producing edge specifying information that is used in the non-selection mode, the edge specifying information taking a first state when the strobe signal is designated to be produced at a first timing and a second state when the strobe signal is designated to be produced at a second timing that is different from the first timing.

11. The method as claimed in claim 10 , further comprising:

issuing a data read command; and

receiving a data signal generated in response to the data read command, the data signal being produced with one of the strobe signal responsive to the selection mode, the strobe signal responsive to the non-selection mode and the first state, and the strobe signal responsive to the non-selection mode and the second state.

12. The method as claimed in claim 11 , wherein the strobe signal responsive to the non-selection mode and the first state is fixed temporarily at a first logic level at the first timing and then changed between the first logic level and a second logic level, and the strobe signal responsive to the non-selection mode and the second state is fixed temporarily at the first logic level at the second timing and then changed between the first logic level and the second logic level.

13. The method as claimed in claim 12 , wherein the strobe signal responsive to the selection mode is fixed temporarily at the first logic level at a third timing and then changed between the first logic level and the second logic level, the third timing being different from each of the first and second timings.

14. The method as claimed in claim 12 , further comprising producing latency information to designate a period of time between issuance of the data read command and production of the data signal.

15. The method as claimed in claim 14 , wherein the producing the synchronous mode information, the producing the edge specifying information, the issuing the data read command and the producing the latency information are performed on a semiconductor memory device, and the data signal and the strobe signal is returned from the semiconductor memory device.

16. The method as claimed in claim 15 , further comprising generating and supplying the system clock signal to the semiconductor memory device.