Method and apparatus for demultiplexer design for multi-edge type LDPC coded modulation
View Patent ↗A method involves receiving an LDPC coded bitstream and demultiplexing the received LDPC coded bitstream using an optimized demultiplexer, the optimized demultiplexer being designed by: substituting Q levels of a constellation mapper by Q parallel binary erasure channels; optimizing a density evolution of erasure probability over said binary erasure channels for a plurality of demultiplexer offsets; and identifying from the plurality of demultiplexer offsets those with a minimum number of check node decoder collisions.
1. A method of demultiplexing a Low Density Parity Check (LDPC) coded bitstream, comprising:
receiving a LDPC coded bitstream; and
demultiplexing the received LDPC coded bitstream using an optimized demultiplexer, the optimized demultiplexer configured to:
substitute Q-levels of a constellation mapper by Q parallel binary erasure channels;
optimizing a density evolution over said binary erasure channels for a plurality of demultiplexer configurations to produce corresponding plurality of optimized demultiplexer configurations; and
identifying from the plurality of optimized demultiplexer configurations those configurations with a minimum number of check node decoder collisions.
2. The method of claim 1 , further comprising providing the output of said demultiplexer as an input to a constellation mapper.
3. The method of claim 2 , wherein said method is used for a DVB-T2 environment.
4. The method of claim 2 , wherein said method is used for cable transmission.
5. The method of claim 2 , wherein said method is used in a terrestrial broadcast environment.
6. An apparatus for demultiplexing a Low Density Parity Check coded bitstream for multi-level modulation by receiving a Low Density Parity Check coded bitstream; and
demultiplexing using an optimized demultiplexer, said optimization circuitry comprising:
circuitry for substituting Q-levels of a constellation mapper by Q parallel binary erasure channels;
processor for optimizing a density evolution over said binary erasure channels for a plurality of demultiplexer configurations to produce corresponding plurality of optimized demultiplexer configurations; and
circuitry for identifying from the plurality of optimized demultiplexer configurations a demultiplexer configuration with a minimum number of check node decoder collisions.
7. The apparatus of claim 6 , wherein said demultiplexer output is provided to a constellation mapper.
8. The apparatus of claim 7 , wherein said apparatus is used in a DVB-T2 environment.
9. The apparatus of claim 7 , wherein said apparatus is used for cable transmission.
10. The apparatus of claim 7 , wherein said apparatus is used in a terrestrial broadcast environment.