Memory device, memory management device, and memory management method
View Patent ↗Disclosed is a memory device which receives a check command and check information from a Central Processing Unit (CPU), reads data written in a predetermined area of a memory based on the check information in response to the check command, and checks a data pattern of the data read based on the check information.
1. A memory device comprising:
a memory array having a data pattern written in a predetermined area of the memory array, the predetermined area having a start address and a size;
a reception unit to receive a check command and check information from a Central Processing Unit (CPU), the check information comprising memory area information, the memory area information comprising the start address and size of to the predetermined area and the data pattern previously written to the predetermined area of the memory array;
a read unit to read data written in the predetermined area of the memory array based on the start address and size of the predetermined area included in the check information and in response to the reception unit receiving the check command; and
a check unit to check the data read based on the check information by comparing the data pattern included in the check information and the data read by the read unit,
wherein the memory device is configured to perform a check of the data written in the predetermined area of the memory array in response to the reception unit receiving the check command.
2. The memory device of claim 1 , wherein the data pattern was written in the predetermined area of the memory array in response to a data write command being sent from the CPU.
3. The memory device of claim 1 , wherein the check unit generates an error message when the data pattern and the data read are inconsistent with each other.
4. The memory device of claim 1 , wherein the memory array is a flash memory.
5. A memory management device comprising:
a control register in which a check command and check information are written by a Central Processing Unit (CPU), the check information comprising a data pattern that was written to a predetermined area of a memory array prior to the check command and check information being written to the control register, the predetermined area having a start address and a size, the check information comprising the start address and the size of the predetermined area;
a read unit to read data written in the predetermined area of the memory array based on the start address and size of the predetermined area included in the check information and in response to the check command when the check command and the check information are written in the control register, wherein the memory array is on a memory device that is separate from the memory management device;
a check unit to check the data read based on the check information by comparing the data pattern included in the check information and the data read by the read unit; and
a status register in which a result of the check performed by the check unit is written.
6. The memory management device of claim 5 , wherein the check unit generates an error message, and writes the error message in the status register when the data pattern and the read data are inconsistent with each.
7. The memory management device of claim 5 , wherein the memory array is a flash memory.
8. The memory management device of claim 5 , wherein the data pattern was written in the predetermined area of the memory array as a result of a data write command being sent from the CPU.
9. A memory management method comprising:
writing a data pattern to a predetermined area of a memory array, the predetermined area having a start address and a size;
receiving a check command and check information from a Central Processing Unit (CPU), the check information comprising the start address and the size of the predetermined area and the data pattern;
reading data written in the predetermined area of a memory array based on the start address and size of the predetermined area included in the check information and in response to receiving the check command; and
checking the data read based on the check information by comparing the data pattern included in the check information and the data read, wherein the checking of the data is performed without accessing the data with the CPU.
10. The method of claim 9 , wherein the checking comprises generating an error message when the data pattern and the read data are inconsistent with each other.
11. The method of claim 9 , wherein the memory array is a flash memory.
12. The method of claim 9 , wherein the writing of the data pattern in the predetermined area of the memory array is performed as a result of a data write command being sent from the CPU.
13. A non-transitory computer readable recording medium storing a program to cause a computer to implement the method of claim 9 .
14. A non-transitory computer readable recording medium storing a program to cause a computer to implement the method of claim 10 .
15. A non-transitory computer readable recording medium storing a program to cause a computer to implement the method of claim 11 .
16. A non-transitory computer readable recording medium storing a program to cause a computer to implement the method of claim 12 .