Programming method and device for a buffer cache in a solid-state disk system
View Patent ↗Provided are a method and apparatus for programming a buffer cache in a Solid State Disk (SSD) system. The buffer cache programming apparatus in the SSD system may include a buffer cache unit to store pages, a memory unit including a plurality of memory chips, and a control unit to select at least one of the page as a victim page, based on a delay occurring when a page is stored in at least one target memory chip among the plurality of memory chips.
1. An apparatus for programming a buffer cache in a Solid State Disk (SSD) system, the apparatus comprising:
a buffer cache unit to store pages;
a memory unit comprising a plurality of memory chips; and
a control unit to select at least one of the pages as a victim page, based on a delay occurring when a page is stored in at least one target memory chip among the plurality of memory chips.
2. The apparatus of claim 1 , wherein the control unit selects the victim page based on a usage frequency of the pages or the most recent usage of the pages.
3. The apparatus of claim 1 , wherein the control unit selects, as the victim page, a page that has not been selected as the victim page, has not been used for a longest time, and is storable in the target memory chip without a delay.
4. The apparatus of claim 3 , wherein a case in which the victim page is delayed corresponds to a case in which the victim page is a partial page, and a memory chip that stores an original page of the victim page is in use.
5. The apparatus of claim 3 , wherein the victim page that is storable without the delay corresponds to a case in which the victim page is the entire page, or a case in which the victim page is a partial page, and a memory chip that stores an original page of the victim page is not in use.
6. The apparatus of claim 1 , wherein the control unit stores an original page of the victim page in the target memory chip by reading the original page and combining the victim page with the original page when the victim page is a partial page, and a memory chip that stores the original page of the victim page is not in use.
7. The apparatus of claim 1 , wherein the control unit stores the victim page in the target memory chip when the victim page is the entire page.
8. The apparatus of claim 1 , wherein the control unit selects, as the target memory chip, a chip having a largest available storage space from idle memory chips in the memory unit before selecting the victim page.
9. The apparatus of claim 1 , wherein the control unit selects a new target memory chip from memory chips in the memory unit when the victim page that is storable without the delay is unavailable as a result of selecting a new victim page.
10. An apparatus of programming a buffer cache in a Solid State Disk (SSD) system, the apparatus comprising:
a buffer cache unit to store pages;
a memory unit comprising at least one memory chip; and
a control unit to select a new victim page until a victim page that is storable without a delay is selected when the victim page that is selected from the pages in the buffer cache unit is delayed to be stored in a target memory chip in the memory unit.
11. The apparatus of claim 10 , wherein the control unit selects, as the victim page or the new victim page, a page that has not been selected as a target to be stored, and has not been used for a longest time, from the pages in the buffer cache unit.
12. The apparatus of claim 10 , wherein a case in which the victim page is delayed corresponds to a case in which the victim page is a partial page, and a memory chip that stores an original page of the victim page is in use.
13. The apparatus of claim 10 , wherein the victim page that is storable without the delay corresponds to a case in which the victim page is the entire page, or a case in which the victim page is a partial page, and a memory chip that stores an original page of the victim page is not in use.
14. The apparatus of claim 10 , wherein the control unit stores an original page of the victim page in the target memory chip by reading the original page and combining the victim page with the original page when the victim page is a partial page, and a memory chip that stores the original page of the victim page is not in use.
15. The apparatus of claim 10 , wherein the control unit selects, as the target memory chip, a chip having a largest available storage space from idle memory chips in the memory unit before selecting the victim page.
16. A method of programming a buffer cache in a Solid State Disk (SSD) system, the method comprising:
selecting a victim page from pages in a buffer cache unit; and
selecting a new victim page until a victim page that is storable without a delay is selected when the victim page is delayed to be stored in a target memory chip in a memory unit.
17. The method of claim 16 , wherein the selecting of the victim page or the selecting of the new victim page comprises selecting, as the victim page or the new victim page, a page that has not been selected as a target to be stored, and has not been used for a longest time, from the pages in the buffer cache unit.
18. The method of claim 16 , wherein a case in which the victim page is delayed corresponds to a case in which the victim page is a partial page, and a memory chip that stores an original page of the victim page is in use.
19. The method of claim 16 , wherein the victim page that is storable without the delay corresponds to a case in which the victim page is the entire page, or a case in which the victim page is a partial page, and a memory chip that stores an original page of the victim page is not in use.
20. The method of claim 16 , further comprising, if the victim page that is storable without the delay is selected:
storing an original page of the victim page in the target memory chip by reading the original page and combining the victim page with the original page when the victim page is a partial page, and a memory chip that stores the original page of the victim page is not in use.