IP Library Granted Patent US 8,344,455
Granted Patent B2
US 8,344,455 · App. 13/149,554 · Granted Jan 1, 2013

Semiconductor device and fabrication method for the same

Assignee: Panasonic Corporation
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Quick Facts
Patent No.
US 8,344,455
App. No.
13/149,554
Filed
May 31, 2011
Granted
Jan 1, 2013
Kind
B2
Art Unit
2893
USPC
257/368
Abstract

The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.

Claims (41)

1. A semiconductor device comprising:

a gate electrode formed on an active region of a substrate;

a first silicon-germanium layer formed in a first recess provided in a portion of the active region on a first side of the gate electrode;

a first silicide layer formed on the first silicon-germanium layer;

a gate interconnect formed on a region of the active region opposite side of the gate electrode to the first silicon-germanium layer;

a second silicide layer formed on the gate interconnect;

a first contact plug connected to the first and second silicide layer;

a first side wall formed on one side surface of the first gate interconnected closer to the first silicon-germanium layer; and

a second side wall formed on another side surface of the gate interconnect opposite to the first silicon-germanium layer, wherein:

the first contact plug is a shared contact plug to connect the first silicon-germanium layer and the gate interconnect, and

a top position of a part of the first side wall which is located under first contact plug is lower than a top position of the second side wall.

2. The semiconductor device of claim 1 , wherein the first contact plug is connected only to a part of the second silicide layer closer to the first silicon-germanium layer in the gate length direction.

3. The semiconductor device of claim 1 , wherein the second silicide layer is thinner than the gate interconnect.

4. The semiconductor device of claim 1 , wherein each of the first and second silicide layer is made of a silicide containing nickel.

5. The semiconductor device of claim 1 , wherein each of the gate electrode and the gate interconnect is made of a polysilicon.

6. The semiconductor device of claim 1 , wherein the first contact plug is made of a material containing tungsten.

7. The semiconductor device of claim 1 , wherein the first silicon-germanium layer is projected from an upper surface of the substrate.

8. The semiconductor device of claim 1 , wherein

the gate electrode is formed on the active region via a gate insulating film,

the gate interconnect is formed on the active region via a insulating film, and

the gate insulating film and the insulating film are made of the same insulating material and have the same thickness.

9. The semiconductor device of claim 1 , wherein the first silicon-germanium layer is a epitaxial layer.

10. The semiconductor device of claim 1 , wherein the first contact plug does not contact with the second side wall.

11. The semiconductor device of claim 1 , wherein the second side wall includes an inner side wall having an L-shaped cross section and an outer side wall formed on the inner side wall.

12. The semiconductor device of claim 1 , wherein a part of a side surface of the gate interconnect which is located under the first contact is not covered by the side wall.

13. The semiconductor device of claim 1 , wherein the first contact plug connected to a side surface of the gate interconnect which is located under the first contact plug.

14. The semiconductor device of claim 1 , further comprising:

a third silicide layer formed on the gate electrode, wherein

the third silicide layer is thinner than the gate electrode.

15. The semiconductor device of claim 1 , further comprising:

a second silicon-germanium layer formed in a second recess provided in a portion of the active region on a second side of the gate electrode; and

a fourth silicide layer formed on the second silicon-germanium layer.

16. The semiconductor device of claim 15 , further comprising:

the second contact plug connected to the fourth silicide layer, wherein

the first contact plug is larger than the second contact plug.

17. The semiconductor device of claim 1 , further comprising:

an underlying insulating film formed on the gate electrode; and

an interlayer insulating film formed on the underlying insulating film, wherein

the interlayer insulating film has a flat top surface, and

the first contact plug is formed to penetrate the interlayer insulating film and the underlying insulating film.

18. The semiconductor device of claim 17 , wherein the underlying insulating film is made of silicon nitride.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PANASONIC CORPORATION
To: PANNOVA SEMIC, LLC
Reel/Frame 036065/0273 →
Priority Claims (1)
JP 2007-282678 · Oct 31, 2007 · national
Continuity (2)
Division 12247518 · Oct 8, 2008
Related Publication 20110227168A1 · Sep 22, 2011