Vertical diodes for non-volatile memory device

1. A method of forming a non-volatile memory device, comprising:

providing a substrate having a surface region;

depositing a first dielectric material overlying the surface region;

forming a first wiring structure overlying the first dielectric material;

depositing a metal oxide material having an n − type impurity characteristic overlying the first wiring structure;

depositing a silicon germanium material having a p+ type impurity characteristic overlying the metal oxide material having the n − type impurity characteristic, wherein a p+n − junction region is formed between the metal oxide material having the n− type impurity characteristic and the silicon germanium material having the p+ type impurity characteristic;

depositing a resistive switching material comprising an amorphous silicon material overlying the silicon germanium material having the p+ type impurity characteristic; and

forming a second wiring structure overlying the resistive switching material, the second wiring structure comprising at least an active metal material in physical and electrical contact with the resistive switching material.

2. The method of claim 1 wherein the metal oxide material comprises a zinc oxide material.

3. The method of claim 2 wherein depositing the zinc oxide material comprises performing by a physical vapor deposition process at a deposition temperature ranging from about 25 Degree Celsius to about 100 Degree Celsius.

4. The method of claim 2 wherein the zinc oxide material has a polycrystalline characteristic.

5. The method of claim 2 wherein depositing the zinc oxide material comprises performing a process selected from a group consisting of: a radio frequency (RF) sputtering process, a reactive sputtering process, or a magnetron sputtering process.

6. The method of claim 1 wherein performing by the physical vapor deposition process comprises using a zinc oxide target material.

7. The method of claim 1 wherein performing by the physical vapor deposition process comprises using zinc as a target material in an oxygen environment.

8. The method of claim 1 wherein the p+ type impurity characteristic is provided by a p+ type impurity selected from a group consisting of: a boron species, an aluminum species, a gallium species.

9. The method of claim 1 wherein depositing the silicon germanium material having the p+ impurity characteristic comprises performing a chemical vapor deposition process using silane or disilane as a silicon precursor, germane as a germanium precursor, and diborane or boron chloride as a boron precursor.

10. The method of claim 9 wherein performing the chemical vapor deposition process is selected from a group consisting of: a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process.

11. The method of claim 1 wherein the second wiring structure further comprises a conductive material selected from a group consisting of: copper, tungsten, aluminum, a doped semiconductor material.

12. The method of claim 1 wherein forming the first wiring structure comprises forming the first wiring structure to have an elongated shape and spatially extending in a first direction;

wherein forming the second wiring structure comprises forming the second wiring structure to have an elongated shape and spatially extending in a second direction; and

wherein the first direction is substantially orthogonal to the second direction.