Metal thin film connection structure, manufacturing method thereof and array substrate

1. A metal thin film connection structure, comprising:

a first metal layer pattern;

a second metal layer pattern which is separately disposed with the first metal layer pattern;

a first insulating layer formed on the first metal layer pattern and the second metal layer pattern;

a plurality of first via holes formed over the first metal layer pattern;

a plurality of second via holes formed over the second metal layer pattern; and

a plurality of third metal layer patterns formed on the first insulating layer, the third metal layer patterns being filled in the first via holes and the second via holes and electrically connect the first metal layer pattern and the second metal layer pattern through the first and second via holes,

wherein the plurality of third metal layer patterns are separately provided.

2. The metal thin film connection structure of claim 1 , wherein the plurality of first via holes are in a stagger arrangement.

3. The metal thin film connection structure of claim 1 , wherein the plurality of second via holes are in a stagger arrangement.

4. The metal thin film connection structure of claim 1 , wherein each of the third metal layer patterns is filled in one of the first via holes and one of the second via holes.

5. The metal thin film connection structure of claim 1 , wherein the third metal layer patterns are of a strip configuration.

6. The metal thin film connection structure of claim 1 , wherein the plurality of third metal layer patterns connecting the first metal layer pattern and the second metal layer pattern are of a parallel connection configuration.

7. The metal thin film connection structure of claim 1 , wherein the first and second metal layer patterns are disposed in the same layer, and the first and second via holes pass through the first insulating layer, respectively.

8. The metal thin film connection structure of claim 1 , further comprising a second insulating layer, wherein the second insulating layer is formed on the first metal layer pattern, the second metal layer is formed on the second insulating layer, the first via holes pass through the first and second insulating layers, and the second via holes pass through the first insulating layer.

9. An array substrate, comprising:

a base substrate; and

a metal thin film connection structure according to claim 1 , the metal thin film connection structure being formed on the base substrate.

10. The array substrate of claim 9 , wherein the first and second metal layer patterns are disposed in the same layer, and the first and second via holes pass through the first insulating layer, respectively.

11. The array substrate of claim 9 , further comprising a second insulating layer, wherein the second insulating layer is formed on the first metal layer pattern, the second metal layer is formed on the second insulating layer, the first via holes pass through the first and second insulating layers, and the second via holes pass through the first insulating layer.

12. The array substrate of claim 9 , wherein each of the third metal layer patterns is filled in one of the first via holes and one of the second via holes.

13. The array substrate of claim 9 , wherein the plurality of first via holes and/or the plurality of second via holes are in a stagger arrangement.

14. The array substrate of claim 9 , wherein the plurality of third metal layer patterns connecting the first metal layer pattern and the second metal layer pattern are of a parallel connection configuration.

15. The array substrate of claim 9 , comprising a pixel region and a wiring region which is at the periphery of the pixel region,

wherein the metal thin film connection structure is formed in the pixel region and/or the wiring region; and the first metal layer pattern is formed of a gate metal layer, and the second metal layer pattern is formed of a data metal layer.

16. The array substrate of claim 9 , comprising a pixel region and a wiring region which is at the periphery of the pixel region, wherein the metal thin film connection structure is formed in the pixel region and/or the wiring region; and the first and second metal layer patterns are disposed in the same layer and formed of a gate metal layer or a gate metal layer.

17. A manufacturing method for a metal thin film connection structure, comprising,

forming a first metal layer pattern and a second metal layer pattern, the first metal layer pattern and the second metal layer pattern are separately disposed;

forming a first insulating layer on the first metal layer pattern and the second metal layer pattern;

forming a plurality of first via holes over the first metal layer pattern;

forming a plurality of second via holes over the second metal layer pattern; and

forming a plurality of third metal layer patterns on the first insulating pattern, the third metal layer patterns being filled in the first via holes and the second via holes and electrically connecting the first metal layer pattern and the second metal layer pattern,

wherein the plurality of third metal layer patterns are separately provided.

18. The manufacturing method for the metal thin film connection structure of claim 17 , wherein the plurality of first via holes and the plurality of second holes are formed simultaneously with a passivation layer of a thin film transistor; and

the third metal layer patterns are formed simultaneously with a pixel electrode of an array substrate.

19. The manufacturing method for the metal thin film connection structure of claim 17 , wherein the first and second metal layer patterns are disposed in the same layer, and the first and second via holes pass through the first insulating layer, respectively.

20. The manufacturing method for the metal thin film connection structure of claim 17 , after forming the first metal layer and before forming the second metal layer, further comprising:

forming a second insulating layer on the first metal layer pattern, wherein the second metal layer pattern is formed on the second insulating layer, the first via holes pass through the first and second insulating layers, and the second via holes pass through the first insulating layer.