Semiconductor device
A semiconductor device in which it is possible to suppress short-circuiting between pads for chip arising from dicing processing is provided. The semiconductor device includes a semiconductor substrate, multiple first pads, and multiple second pads. The first pads are formed in an element formation region and the second pads are formed in a dicing line region surrounding the element formation region. The dicing line region includes a first region for which second pads are prone to electrically short-circuit to each other and a second region for which second pads are less prone to electrically short-circuit to each other. Some first pads arranged in positions opposite the first region are arranged farther away from one side of the outer edge of the element formation region than the remaining first pads arranged in positions opposite the second region are.
1. A semiconductor device comprising:
a semiconductor substrate having a main surface and having in the main surface an element formation region and a dicing line region surrounding the element formation region;
a plurality of first pads formed in the element formation region; and
a plurality of second pads formed in the dicing line region,
wherein the first pads and the second pads are arranged across each other along a first edge of the element formation region,
wherein a first distance is a closest distance between a third pad of the first pads and the first edge of the element formation region,
a second distance is a closest distance between a fourth pad of the first pads and the first edge of the element formation region,
a third distance is a closest distance between a fifth pad of the second pads closest with the third pad and the first edge of the element formation region,
a fourth distance is a closest distance between a sixth pad of the second pads closest with the fourth pad and the first edge of the element formation region,
the third distance and the fourth distance are substantially the same distance,
the third pad is aligned with the fifth pad across the first edge of the element formation region with no intervening first pads therebetween and the fourth pad is aligned with the sixth pad across the first edge of the element formation region with no intervening first pads therebetween, and
the first distance is longer than the second distance.
2. A semiconductor device according to claim 1 , wherein there is a long signal line in the dicing line region near the third pad, and
there is no long signal line in the dicing line region near the fourth pad.
3. A semiconductor device according to claim 1 , wherein there is a circuit for evaluation in the dicing line region near the third pad, and
there is no circuit for the evaluation in the dicing line region near the fourth pad.
4. The semiconductor device according to claim 1 , wherein each of the first pads is arranged with the same pitch.
5. The semiconductor device according to claim 1 , wherein the arrangement pitch of some first pads is larger than the arrangement pitch of the remaining first pads.
6. The semiconductor device according to claim 1 , wherein each of the first pads is arranged at the same intervals.
7. The semiconductor device according to claim 1 , wherein the intervals at which some first pads are arranged are longer than the intervals at which the remaining first pads are arranged.
8. The semiconductor device according to claim 1 , wherein each of the first pads has a planar shape in the same size.
9. The semiconductor device according to claim 2 , wherein the distance between some first pads and the first edge is longer than the distance between the remaining first pads and the first edge.