Static memory cell having independent data holding voltage
View Patent ↗A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.
1. A semiconductor device comprising:
a memory cell including a first inverter having an input coupled to a first storage node and an output coupled to a second storage node, a second inverter having an input coupled to the second storage node and an output coupled to the first storage node, a first transistor coupled to the first storage node and a second transistor coupled to the second storage node, the first and second inverters each receiving a power supply voltage and a reference voltage lower than the power supply voltage;
a word line coupled to gates of the first and second transistors;
a data line pair, one of which is coupled to the first transistor and the other of which is coupled to the second transistor;
a power supply line coupled to the first and second inverters and providing the power supply voltage;
a third transistor having a source-drain path between the power supply line and a first node to which a first potential is applied;
a fourth transistor having a source-drain path between the power supply line and a second node to which a second potential lower than the first potential is applied,
wherein signals are applied to gates of the third and fourth transistors to establish a first state that the third and fourth transistors are made conductive and non-conductive, respectively, and a second state that the third and fourth transistors are made non-conductive and conductive, respectively; and
the semiconductor device further comprising a driver providing the word line with a voltage lower than the first potential to make the first and second transistors both conductive.
2. A semiconductor device according to claim 1 , wherein the first and second transistors are n-type transistors and the third and fourth transistors are p-type transistors.
3. A semiconductor device comprising:
a memory cell including a first inverter having an input coupled to a first storage node and an output coupled to a second storage node, a second inverter having an input coupled to the second storage node and an output coupled to the first storage node, a first transistor coupled to the first storage node and a second transistor coupled to the second storage node, the first and second inverters each receiving a power supply voltage and a reference voltage lower than the power supply voltage;
a word line coupled to gates of the first and second transistors;
a data line pair, one of which is coupled to the first transistor and the other of which is coupled to the second transistor;
a power supply line coupled to the first and second inverters and providing the power supply voltage;
a third transistor having a source-drain path between the power supply line and a first node to which a first potential is applied;
a clamp circuit coupled between the power supply line and a second node to which a second potential lower than the first potential is applied,
wherein a signal is applied to a gate of the third transistor to establish a first state that the third transistor is made conductive and a second state that the third transistor is made non-conductive; and
the semiconductor device further comprising a driver providing the word line with a voltage lower than the first potential to make the first and second transistors both conductive.
4. A semiconductor device according to claim 3 , wherein the first and second transistors are n-type transistors and the third transistor is a p-type transistor.