Voltage ramp circuitry and voltage ramp methods for voltage regulators

1. A method of adjusting a voltage, comprising:

producing a voltage ramp starting at a first voltage and ending at a second voltage;

compensating the voltage ramp according to a compensation parameter, wherein the compensation parameter is configured to compensate for a circuit parameter;

outputting a voltage according to the compensated voltage ramp; and

compensating the voltage ramp for a second compensation parameter,

wherein at least one of:

the first compensation parameter is applied and substantially optimized for a positively-sloped voltage ramp and the second compensation parameter is substantially optimized for a negatively-sloped voltage ramp; and

the first compensation parameter corresponds to an output capacitor equivalent series resistance voltage drop and the second circuit parameter corresponds to an output capacitor current.

2. The method of claim 1 , further comprising modifying PWM (pulse width modulation) pulses to increase a slew rate of the voltage ramp.

3. The method of claim 1 , further comprising modifying a current limit according to the compensated voltage ramp.

4. The method of claim 1 , wherein the output capacitor current comprises a scaled output capacitor current.

5. The method of claim 1 , further comprising adding a post-ramp offset to an end of the voltage ramp.

6. The method of claim 5 , wherein the post-ramp offset comprises a programmable amplitude offset and a programmable duration offset.

7. The method of claim 5 , wherein the post-ramp offset further comprises a slow decay.

8. The method of claim 5 , wherein the post-ramp offset comprises:

a first post-ramp offset configured to be applied to a positively-sloped voltage ramp; and

a second post-ramp offset configured to be applied to a negatively-sloped voltage ramp.

9. The method of claim 1 , wherein the compensation parameter is further configured to control a lag in a change in output voltage.

10. The method of claim 1 , wherein the compensation parameter is further configured to control an output voltage overshoot.

11. The method of claim 1 , wherein the compensation parameter is further configured to control an output voltage undershoot.

12. The method of claim 1 , further comprising updating a voltage regulator control loop parameter according to the compensated voltage ramp.

13. The method of claim 1 , further comprising modifying an ATR (active transient response) threshold according to the compensated voltage ramp.

14. A voltage ramp circuit comprising:

a voltage ramp generator configured to output a voltage ramp starting at a first voltage and ending at a second voltage; and

a compensation circuit responsive to the voltage ramp generator, wherein the compensation circuit is configured to modify the voltage ramp according to a circuit parameter,

wherein the compensation circuit comprises a capacitor current compensation circuit configured to compensate for an output capacitor current.

15. The voltage ramp circuit of claim 14 , wherein the compensation circuit comprises a post-ramp offset circuit configured to add a programmable amplitude and duration offset to an end of the voltage ramp.

16. The voltage ramp circuit of claim 15 , wherein the programmable amplitude and duration offset according to whether the voltage ramp is positively-sloped or negatively sloped.

17. The voltage ramp circuit of claim 14 , wherein the compensation circuit comprises an ESR compensation circuit configured to compensate for a voltage drop across an output capacitor.

18. The voltage ramp circuit of claim 14 , wherein the capacitor current compensation circuit is configured to subtract the output capacitor current from a sensed output current.

19. The voltage ramp circuit of claim 14 , wherein the capacitor current compensation circuit is further configured to be scaled by a programmable constant wherein the programmable constant is configured to:

control a voltage overshoot/undershoot; and

control a rate of the voltage ramp.

20. The voltage ramp circuit of claim 19 , wherein the programmable constant comprises a first constant for an up transient and a second constant for a down transient.

21. A voltage ramp circuit, comprising:

a voltage ramp generator configured to output a voltage ramp starting at a first voltage and ending at a second voltage; and

a compensation circuit comprising:

an ESR compensation circuit configured to adjust the voltage ramp according to a voltage drop across an output capacitor;

an output capacitor current compensation circuit configured to adjust the voltage ramp according to an output capacitor current; and

a post-ramp offset circuit.

22. The voltage ramp circuit of claim 21 , wherein the capacitor current compensation circuit is further configured to be scaled by a programmable constant wherein the programmable constant is configured to:

control a voltage overshoot/undershoot; and

control a rate of the voltage ramp.

23. The voltage ramp circuit of claim 22 , wherein the programmable constant is selected from a first programmable constant for an up-ramp and a second programmable constant for a down-ramp.

24. The voltage ramp circuit of claim 21 , wherein the post-ramp offset circuit is configured to generate an amplitude offset and a duration offset.

25. The voltage ramp circuit of claim 24 , wherein the amplitude offset and the duration offset are programmable.

26. The voltage ramp circuit of claim 21 , further comprising a circuit parameter modification circuit.

27. The voltage ramp circuit of claim 26 , wherein the circuit parameter modification circuit is configured to adjust a voltage regulator control loop parameter.

28. The voltage ramp circuit of claim 26 , wherein the circuit parameter modification circuit is configured to adjust an ATR (active transient response) threshold.

29. The voltage ramp circuit of claim 26 , wherein the circuit parameter modification circuit is configured to control a PWM (pulse width modulation) pulse.

30. The voltage ramp circuit of claim 26 , wherein the circuit parameter modification circuit is configured to modify a current limit.