Compensating for wander in AC coupling data interface
Techniques are disclosed relating to reducing wander created by AC couplers. In one embodiment, an integrated circuit is disclosed that includes an AC coupler and a DC-level shifter. The AC coupler is configured to receive a differential input signal at first and second nodes, and to shift a common-mode voltage of the differential input signal. The DC-level shifter is coupled to the first and second nodes, and configured to reduce wander of the AC coupler. In various embodiments, the DC-level shifter is configured to supply a differential reference signal to the AC coupler, and to create the differential reference signal from the differential input signal at the first and second nodes by changing a common-mode voltage of the differential input signal.
1. An integrated circuit, comprising:
an AC coupler configured to receive a differential input signal at first and second nodes, wherein the AC coupler is configured to shift a common-mode voltage of the differential input signal;
a DC-level shifter, wherein the DC-level shifter includes a resistor divider network coupled to the first and second nodes and to a voltage supply, wherein the DC-level shifter is configured to reduce wander of the AC coupler; and
wherein the DC-level shifter and the AC coupler form a feedforward path.
2. The integrated circuit of claim 1 , wherein the DC-level shifter is configured to supply a differential reference signal to the AC coupler, wherein the DC-level shifter is configured to create the differential reference signal from the differential input signal at the first and second nodes by changing a common-mode voltage of the differential input signal.
3. The integrated circuit of claim 2 , wherein the AC coupler is configured to low-pass filter the differential reference signal, and to add the low-pass-filtered differential reference signal to a high-pass-filtered form of the differential input signal.
4. The integrated circuit of claim 2 , wherein the resistor divider network is configured to change the common-mode voltage of the differential input signal.
5. The integrated circuit of claim 2 , wherein the DC-level shifter includes first and second current sources configured to supply current to increase the common-mode voltage of differential input signal to create the differential reference signal.
6. The integrated circuit of claim 2 , wherein the DC-level shifter includes an amplifier configured to increase the common-mode voltage of the differential input signal to create the differential reference signal.
7. The integrated circuit of claim 1 , further comprising:
a linear equalizer coupled to the AC coupler;
wherein the apparatus is configured to match a gain of the DC-level shifter with a low-frequency gain of the linear equalizer.
8. The integrated circuit of claim 7 , wherein the apparatus is configured to adjust resistance in the DC-level shifter to match the gain of the DC-level shifter with the low-frequency gain of the linear equalizer.
9. An apparatus, comprising:
a receiver configured to use an AC coupler to high-pass filter a differential input signal;
wherein the receiver is configured to use a DC-level shifter to compensate for wander of the AC coupler by adding a filtered differential reference signal to the high-pass-filtered differential input signal to produce a differential output signal, wherein DC-level shifter includes a resistor divider network coupled to the AC coupler; and
wherein the DC-level shifter and the AC coupler form a feedforward path.
10. The apparatus of claim 9 , wherein the DC-level shifter is configured to create the filtered differential reference signal by shifting a common-mode voltage of the differential input signal and low-pass filtering the differential input signal.
11. The apparatus of claim 10 , wherein the receiver is configured to use an amplifier to amply the differential output signal, and wherein the common-mode voltage is a common-mode voltage supported by the amplifier.
12. The apparatus of claim 10 , wherein the resistor divider network is configured to shift the common-mode voltage of the differential input signal.
13. The apparatus of claim 9 , wherein the receiver is configured to low-pass filter the differential input signal by using a resistor capacitor (RC) circuit.
14. The apparatus of claim 9 , wherein the receiver includes a linear equalizer configured to equalize the differential input signal, and wherein the receiver is configured to create the filtered differential reference signal by adjusting a differential voltage of the differential input signal based on a low-frequency gain of the linear equalizer.
15. The apparatus of claim 9 , wherein the receiver is configured to communicate via a PCI Express standard.
16. A method, comprising:
an AC coupler of a receiver high-pass filtering a differential input signal;
a DC-level shifter of the receiver reducing wander created by the AC coupler by adding, to the high-pass-filtered differential input signal, a low-pass-filtered form of the differential input signal that has a shifted common-mode voltage, wherein the reducing includes a resistor divider network of the DC-level shifter shifting the common-mode voltage of the differential input signal to create the low-pass-filtered form of the differential input signal; and
wherein the DC-level shifter and the AC coupler form a feedforward path.
17. The method of claim 16 , further comprising:
the receiver changing a differential voltage of the differential input signal to create the low-pass-filtered form of the differential input signal, wherein the differential voltage is changed based on a low-frequency gain of a linear equalizer in the receiver.
18. An apparatus, comprising:
an AC coupler configured to receive a differential input signal at first and second nodes, and to shift a common-mode voltage of a differential input signal; and
a means for reducing wander of the AC coupler, wherein the means for reducing wander includes a resistor divider network; and
wherein the means for reducing wander and the AC coupler form a feedforward path.
19. The apparatus of claim 18 , further comprising:
a linear equalizer coupled to the AC coupler, wherein the linear equalizer is configured to equalize the differential input signal.
20. A non-transitory computer readable medium comprising a data structure which is operated upon by a program executable on a computer system, the program operating on the data structure to perform a portion of a process to fabricate an integrated circuit including circuitry described by the data structure, the circuitry described by the data structure including:
an AC coupler configured to receive a differential input signal at first and second nodes, wherein the AC coupler is configured to shift a common-mode voltage of the differential input signal;
a DC-level shifter, wherein the DC-level shifter includes a resistor divider network coupled to the first and second nodes and to a voltage supply, wherein the DC-level shifter is configured to reduce wander of the AC coupler; and
wherein the DC-level shifter and the AC coupler form a feedforward path.
21. The computer readable medium of 20 , wherein the storage medium stores hardware description language (HDL) data, Verilog data, or graphic database system II (GDSII) data.