System and methods to improve the performance of semiconductor based sampling system
Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch.
1. A sampling circuit that operates in at least a sample state and a hold state comprising:
an input terminal receiving a time variable input signal;
a semiconductor switch that operates in at least a non-conductive mode and a conductive mode as directed by an amount of charge applied to a control terminal, the semiconductor switch being coupled between the input terminal and an output terminal, the semiconductor switch body being accessible at a body bias terminal;
a control circuit that is non-coupled to the input terminal and coupled to the control terminal and operative to select the semiconductor switch operation mode; and
a body bias circuit coupled between the body bias terminal and the input terminal or the output terminal that maintains, in sample and hold states, respectively, a predetermined and substantially constant body bias voltage difference between the body bias terminal and at least one of (i) the input terminal or (ii) the output terminal,
wherein the body bias circuit comprises a charge refresh circuit operating in one or the other of a first phase and a second phase, selectively, and a first body bias capacitor coupled between the body bias terminal and the input terminal or the output terminal.
2. The sampling circuit of claim 1 , wherein the charge refresh circuit operating phases are synchronized with the sampling circuit sample and hold states.
3. The sampling circuit of claim 1 , wherein the body bias voltage is selected based at least in part on the magnitude of the signal received at the input terminal.
4. The sampling circuit of claim 1 , wherein during the hold state the control circuit is operative to establish a substantially zero voltage difference between the control terminal and the body bias terminal.
5. The sampling circuit of claim 1 , wherein the amplitude of a control voltage swing at the control terminal that effects the transition of the sampling circuit from a hold state to a sample state is substantially constant.
6. The sampling circuit of claim 1 , wherein the amplitude of a control voltage swing at the control terminal that effects the transition of the sampling circuit from a sample state to a hold state is substantially constant.
7. The sampling circuit of claim 1 , wherein the first body bias capacitor has a first terminal and a second terminal, and is coupled between the input terminal and the body bias terminal, and the body bias circuit further comprises:
a second body bias capacitor having a first terminal and a second terminal and coupled in parallel with the first body bias capacitor;
a first bias body bias switch coupled between the second terminal of the first body bias capacitor and the second terminal of the second body bias capacitor;
a second body bias switch coupled between the first terminal of the first body bias capacitor and the first terminal of the second body bias capacitor;
a third body bias switch coupled between the second terminal of the second body bias capacitor and a ground; and
a fourth body bias switch coupled between the first terminal of the second body bias capacitor and a bias node; and
the control circuit is adapted to control the first, second, third, and fourth body bias switches.