Display substrate and method of manufacturing the same
View Patent ↗A display substrate having a low resistance signal line and a method of manufacturing the display substrate are provided. The display substrate includes an insulation substrate, a gate line, a data line and a pixel electrode. The gate line gate line is formed through a sub-trench and an opening portion. The sub-trench is formed in the insulation substrate and the opening portion is formed through a planarization layer on the insulation substrate at a position corresponding to the position of the sub-trench. The data line crosses the gate line. The pixel electrode is electrically connected to the gate line and the data line through a switching element. Thus, a signal line is formed through a trench formed by using a planarization layer and an insulation substrate, so that a resistance of the signal line may be reduced.
1. A method of manufacturing a display substrate, the method comprising:
forming a planarization layer on an insulation substrate;
forming a photoresist pattern on the planarization layer;
etching the planarization layer and a portion of the insulation substrate that are exposed by the photoresist pattern to form an opening portion and a sub-trench, the opening portion corresponding to the planarization layer and the sub-trench formed in the insulation substrate at a position corresponding to a position of the opening portion;
forming a gate line through the opening portion and the sub-trench;
forming a data line crossing the gate line; and
forming a pixel electrode electrically connected to the gate line and the data line.
2. The method of claim 1 , wherein forming the sub-trench comprises:
dry-etching the planarization layer and the insulation substrate by using an etching gas.
3. The method of claim 2 , wherein forming the sub-trench further comprises:
etching an edge portion of the sub-trench by using an etching solution.
4. The method of claim 1 , wherein forming the gate line comprises:
coating a metal paste on a surface of a planarization layer having the opening portion formed thereon, which is disposed on an insulation substrate in which the sub-trench is formed; and
blading the metal paste to insert the metal paste through the opening portion and the sub-trench.
5. The method of claim 4 , wherein the photoresist pattern is removed before the gate line is formed.
6. The method of claim 1 , wherein forming the gate line further comprises:
partially etching surfaces of the gate line and the planarization layer.
7. The method of claim 6 , wherein partially etching the surfaces of the gate line and the planarization layer is performed by a dry-etching process.
8. The method of claim 6 , further comprising:
forming a protection metal layer on the planarization layer before the photoresist pattern is formed; and
wet-etching the protection metal layer by using the photoresist pattern as an etch stop layer.
9. The method of claim 8 , wherein forming the sub-trench comprises:
etching the planarization layer and the insulation substrate by using the photoresist pattern and the etched metal layer as an etch stop layer.
10. The method of claim 9 , wherein the etched protection metal layer is removed while the surfaces of the gate line and the planarization layer are partially etched.
11. The method of claim 1 , wherein an inclined surface of the opening portion is no less than about 0 degree to no more than about 30 degrees with respect to a normal of the surface of the planarization layer.
12. The method of claim 1 , further comprising:
forming a gate insulation layer making a direct contact with the gate line and the planarization layer, respectively, before the data line is formed.