Data storage device comprising dual mode independent/parallel voltage regulators
View Patent ↗A data storage device (DSD) is disclosed comprising a non-volatile memory (NVM), and control circuitry comprising a first voltage regulator having a first output operable to generate a first current, and a second voltage regulator having a second output operable to generate a second current. When in an independent mode, the first current is operable to supply a first load independent of the second current, and the second current is operable to supply a second load independent of the first current. When in a parallel mode, the second output is coupled to the first output in order to increase the first current supplied to the first load and decrease the second current supplied to the second load.
1. A data storage device (DSD) comprising:
a non-volatile memory (NVM); and
control circuitry comprising:
a first voltage regulator comprising a first output operable to generate a first current;
a second voltage regulator comprising a second output operable to generate a second current; and
configuration circuitry for configuring the first and second voltage regulators into one of an independent mode and a parallel mode, wherein:
when in the independent mode, the first current is operable to supply a first load independent of the second current, and the second current is operable to supply a second load independent of the first current; and
when in the parallel mode, the second output is coupled to the first output in order to increase the first current supplied to the first load and decrease the second current supplied to the second load,
wherein:
the first voltage regulator comprises a first switching regulator comprising first switching logic;
the second voltage regulator comprises a second switching regulator comprising second switching logic;
when in the independent mode, the first switching logic is configured to control the first switching regulator and the second switching logic is configured to control the second switching regulator; and
when in the parallel mode, the first switching logic is configured to control the first switching regulator and the second switching regulator.
2. The data storage device as recited in claim 1 , wherein when in the parallel mode the second current is substantially zero.
3. The data storage device as recited in claim 1 , wherein the configuration circuitry comprises programmable switches.
4. The data storage device as recited in claim 1 , wherein the configuration circuitry comprises a fabricated trace.
5. The data storage device as recited in claim 1 , wherein:
the first switching regulator comprises a first periodic switch signal; and
the second switching regulator comprises a second periodic switch signal.
6. The data storage device as recited in claim 5 , wherein the first and second switch signals are in-phase.
7. The data storage device as recited in claim 5 , wherein the first and second switch signals are out-of-phase.
8. The data storage device as recited in claim 1 , wherein the NVM comprises a disk.
9. The data storage device as recited in claim 1 , wherein the NVM comprises a non-volatile semiconductor memory.
10. A method of operating data storage devices (DSDs), each DSD comprising a non-volatile memory (NVM) and control circuitry comprising:
a first voltage regulator comprising a first output operable to generate a first current; and
a second voltage regulator comprising a second output operable to generate a second current;
the method comprising:
when in an independent mode, supplying a first load with the first current independent of the second current, and supplying a second load with the second current independent of the first current; and
when in a parallel mode, coupling the second output to the first output in order to increase the first current supplied to the first load and decrease the second current supplied to the second load,
wherein:
the first voltage regulator comprises a first switching regulator comprising first switching logic;
the second voltage regulator comprises a second switching regulator comprising second switching logic;
when in the independent mode, the first switching logic is configured to control the first switching regulator and the second switching logic is configured to control the second switching regulator; and
when in the parallel mode, the first switching logic is configured to control the first switching regulator and the second switching regulator.
11. The method as recited in claim 10 , wherein when in the parallel mode the second current is substantially zero.
12. The method as recited in claim 10 , wherein coupling the second output to the first output comprises configuring switches.
13. The method as recited in claim 10 , wherein coupling the second output to the first output comprises fabricating a trace.
14. The method as recited in claim 10 , wherein:
the first switching regulator comprises a first periodic switch signal; and
the second switching regulator comprises a second periodic switch signal.
15. The method as recited in claim 14 , wherein the first and second switch signals are in-phase.
16. The method as recited in claim 14 , wherein the first and second switch signals are out-of-phase.
17. The method as recited in claim 10 , wherein the NVM comprises a disk.
18. The method as recited in claim 10 , wherein the NVM comprises a non-volatile semiconductor memory.
19. A power circuit comprising:
a first voltage regulator comprising a first output operable to generate a first current;
a second voltage regulator comprising a second output operable to generate a second current; and
configuration circuitry for configuring the first and second voltage regulators into one of an independent mode and a parallel mode, wherein:
when in the independent mode, the first current is operable to supply a first load independent of the second current, and the second current is operable to supply a second load independent of the first current; and
when in the parallel mode, the second output is coupled to the first output in order to increase the first current supplied to the first load and decrease the second current supplied to the second load,
wherein:
the first voltage regulator comprises a first switching regulator comprising first switching logic;
the second voltage regulator comprises a second switching regulator comprising second switching logic;
when in the independent mode, the first switching logic is configured to control the first switching regulator and the second switching logic is configured to control the second switching regulator; and
when in the parallel mode, the first switching logic is configured to control the first switching regulator and the second switching regulator.
20. The power circuit as recited in claim 19 , wherein:
the first switching regulator comprises a first periodic switch signal; and
the second switching regulator comprises a second periodic switch signal.
21. The power circuit as recited in claim 20 , wherein the first and second switch signals are in-phase.
22. The power circuit as recited in claim 20 , wherein the first and second switch signals are out-of-phase.