Enhancement mode group III-V high electron mobility transistor (HEMT) and method for fabrication
View Patent ↗According to one disclosed embodiment, an enhancement mode high electron mobility transistor (HEMT) comprises a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body, and a gate structure formed over the group III-V barrier layer and including a P type group III-V gate layer. The P type group III-V gate layer prevents a two dimensional electron gas (2 DEG) from being formed under the gate structure. One embodiment of a method for fabricating such an enhancement mode HEMT comprises providing a substrate, forming a group III-V semiconductor body over the substrate, forming a group III-V barrier layer over the group III-V semiconductor body, and forming a gate structure including the P type group III-V gate layer over the group III-V barrier layer.
1. An enhancement mode high electron mobility transistor (HEMT) comprising:
a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body;
a gate structure formed over said group III-V barrier layer, said gate structure including a P type group III-V gate layer formed on said group III-V barrier layer, and one of a conductive gate electrode and a gate dielectric formed directly on said P type group III-V gate layer, wherein said P type group III-V gate layer prevents a two dimensional electron gas (2DEG) from being formed in said heterojunction under said gate structure.
2. The enhancement mode HEMT of claim 1 , wherein said heterojunction comprises a III-nitride heterojunction.
3. The enhancement mode HEMT of claim 1 , wherein said P type group III-V gate layer comprises a P type III-nitride material.
4. The enhancement mode HEMT of claim 1 , wherein said conductive gate electrode is formed on said P type group III-V gate layer.
5. The enhancement mode HEMT of claim 1 , wherein said conductive gate electrode is selected from the group consisting of titanium (Ti), aluminum (Al), and doped polysilicon.
6. The enhancement mode HEMT of claim 1 , wherein said gate dielectric is formed on said P type group III-V gate layer.
7. The enhancement mode HEMT of claim 1 , wherein said gate dielectric is selected from the group consisting of aluminum oxide (Al 2 O 3 ), silicon nitride (Si 3 N 4 ), and silicon dioxide (SiO 2 ).
8. The enhancement mode HEMT of claim 1 , wherein said group III-V semiconductor body comprises gallium nitride (GaN).
9. The enhancement mode HEMT of claim 1 , wherein said group III-V barrier layer comprises aluminum gallium nitride (AlGaN).
10. The enhancement mode HEMT of claim 1 , wherein said group III-V semiconductor body is formed over a substrate, and further comprising a transition structure for reducing a lattice mismatch between said substrate and said group III-V semiconductor body.
11. The enhancement mode HEMT of claim 1 , wherein said group III-V semiconductor body is formed over a substrate selected from the group consisting of silicon (Si), silicon carbide (SiC), and sapphire.
12. A method for fabricating an enhancement mode high electron mobility transistor (HEMT), said method comprising:
forming a group III-V semiconductor body over a substrate;
forming a group III-V barrier layer over said group III-V semiconductor body;
forming a gate structure over said group III-V barrier layer to prevent a two dimensional electron gas (2DEG) from being formed under said gate structure;
said gate structure including a P type group III-V gate layer formed on said group III-V barrier layer, and one of a conductive gate electrode and a gate dielectric formed directly on said P type group III-V gate layer.
13. The method of claim 12 , wherein forming said gate structure further comprises:
forming a mask over said group III-V barrier layer;
creating an opening in said mask to expose a portion of said group III-V barrier layer;
forming said P type group III-V gate layer in said opening.
14. The method of claim 12 , wherein forming said gate structure further comprises:
forming a hard mask over said group III-V barrier layer;
creating an opening in said hard mask to expose a portion of said group III-V barrier layer;
forming said P type group III-V gate layer in said opening.
15. The method of claim 12 , wherein said P type group III-V gate layer is formed using a metalorganic chemical vapor deposition (MOCVD) process.
16. The method of claim 12 , wherein said P type group III-V gate layer comprises a P type III-nitride material.
17. The method of claim 12 , further comprising forming a transition structure over said substrate before forming said group III-V semiconductor body, said transition structure reducing a lattice mismatch between said substrate and said group III-V semiconductor body.
18. The method of claim 12 , wherein forming said gate structure comprises forming said gate dielectric on said P type group III-V gate layer, and further comprises forming said conductive gate electrode over said gate dielectric.
19. The method of claim 12 , wherein said enhancement mode HEMT comprises a III-nitride HEMT.
20. The method of claim 12 , wherein forming said group III-V barrier layer over said group III-V semiconductor body comprises forming an aluminum gallium nitride (AlGaN) barrier layer over a gallium nitride (GaN) semiconductor body.