Granted Patent B2

US 8,625,353 · App. 13/162,520 · Granted Jan 7, 2014

Abstract

Claims (47)

1. An apparatus, comprising:

a plurality of flash memory devices, wherein each flash memory device of the plurality of flash memory devices is arranged to be powered by a power supply voltage, wherein each flash memory device of the plurality of flash memory devices includes a random access memory,

wherein a first subset of the plurality of flash memory devices is configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory device of the first subset of flash memory devices performs actions, including:

loading the random access memory with instructions for the each flash memory device of the first subset of flash memory devices,

executing a first portion of the instructions for the each flash memory device of the first subset of flash memory devices,

after executing the first portion of the instructions for the each flash memory device of the first subset of flash memory devices, employing a countdown timer to wait for a first delay period after executing the first portion of the instructions for the each flash memory device of the first subset of flash memory devices, and

after waiting for the first delay period, executing a second portion of the instructions for the each flash memory device of the first subset of flash memory devices, and

wherein a second subset of the plurality of flash memory devices is configured such that, upon the power supply voltage reaching the pre-determined level, each flash memory device of the second subset of the plurality of flash memory devices performs actions, including:

loading the random access memory with instructions for the each flash memory device of the second subset of flash memory devices,

executing a first portion of the instructions for the each flash memory device of the second subset of flash memory deivces,

after executing the first portion of the instructions for the each flash memory device of the second subset of flash memory devices, employing another countdown timer to wait for a second delay period after executing the first portion of the instructions for the each flash memory device of the second subset of flash memory devices, wherein the second delay period is different than the first delay period, and

after waiting for the second delay period, executing a second portion of the instructions for the each flash memory device of the second subset of flash memory devices.

2. The apparatus of claim 1 , wherein

one or more additional subsets of the plurality of flash memory devices is configured such that, upon the power supply voltage reaching the pre-determined level, each flash memory device of the one or more additional subsets of the plurality of flash memory devices performs actions, including:

loading the random access memory with instructions for the flash memory device,

executing a first portion of the instructions for the flash memory device,

after executing the first portion of the instructions for the flash memory device, employing another countdown timer to wait for a corresponding delay period after executing the first portion of the instructions for the flash memory device, wherein the corresponding delay period for each of the subsets of the plurality of flash memory devices is different from the delay period for each other of the subsets of the plurality of flash memory devices, and

after waiting for the corresponding delay period, executing a second portion of the instructions for the flash memory device.

3. The apparatus of claim 1 , wherein

the plurality of flash memory devices are arranged in columns, each column has a corresponding integer column number, the first subset of the plurality of flash memory devices consists of each of the flash memory devices in the first column, the second subset of the plurality of flash memory devices consists of each of the flash memory devices in the second column, the first delay period is a multiple of the column number of the first column and a unit delay period, and wherein the second delay period is a multiple of the column number of the second column and the unit delay period.

4. The apparatus of claim 1 , further comprising:

a motherboard; and

a power supply that is arranged to provide the power supply voltage to each flash memory device of the plurality of flash memory devices via the motherboard.

5. The apparatus of claim 1 , wherein each flash memory device includes a plurality of memory cells including a trim sector that is inaccessible by normal addressing; wherein the trim sector stores a bad sector map, a program verify point, and an erase verify point; wherein the trim sector of each flash memory device in the first subset of flash memory devices further includes a script that, when loaded into the random access memory, causes the flash memory device to employ the countdown timer to wait for the first delay period after executing the first portion of the instructions for the flash memory device; and wherein the trim sector of each flash memory device in the second subset of flash memory devices includes a script that, when loaded into the random access memory, causes the flash memory device to employ the another countdown timer to wait for the second delay period after executing the first portion of the instructions for the flash memory device.

6. The apparatus of claim 1 , wherein each flash memory device of the plurality of flash memory devices includes a controller component, a decoder component, and a plurality of memory cells.

7. The apparatus of claim 6 , wherein each of the controller components includes means for controlling accesses to the memory cells, wherein each of the decoder components includes means for decoding, or wherein each of the memory cells includes means for storing at least one bit.

8. A method, comprising:

each flash memory device of a plurality of flash memory devices receiving a power supply voltage, wherein each flash memory device of the plurality of flash memory devices includes a random access memory,

each flash memory device in a first subset of the plurality of flash memory devices, upon the power supply voltage reaching a pre-determined level:

loading the random access memory with instructions for the each flash memory device of the first subset of flash memory devices,

executing a first portion of the instructions for the each flash memory device of the first subset of flash memory devices,

after executing the first portion of the instructions for the each flash memory device of the first subset of flash memory devices, employing a countdown timer to wait for a first delay period after executing the first portion of the instructions for the each flash memory device of the first subset of flash memory devices, and

after waiting for the first delay period, executing a second portion of the instructions for the each flash memory device of the first subset of flash memory devices, and

each flash memory device in a second subset of the plurality of flash memory devices, upon the power supply voltage reaching the pre-determined level:

loading the random access memory with instructions for the each flash memory device of the second subset of flash memory devices,

executing a first portion of the instructions for the each flash memory device of the second subset of flash memory devices,

after executing the first portion of the instructions for the each flash memory device of the second subset of flash memory devices, employing another countdown timer to wait for a second delay period after executing the first portion of the instructions for the each flash memory device of the second subset of flash memory devices, wherein the second delay period is different than the first delay period, and

after waiting for the second delay period, executing a second portion of the instructions for the each flash memory device of the second subset of flash memory devices.

9. A tangible processor-readable medium having processor-executable code encoded therein, which, upon execution by one or more processors, enables actions, comprising:

upon a power supply voltage reaching a pre-determined level:

executing a first portion of instructions for a flash memory device,

after executing the first portion of the instructions for the flash memory device, employing a countdown timer to wait for a delay period after executing the first portion of the instructions for the flash memory device, wherein the delay period is such that other flash memory devices receiving the power supply voltage start in a staggered manner relative to each other such that:

either:

the delay period is a non-random pre-determined delay period that is distinct from a delay period associated with at least a portion of the other flash memory devices receiving the power supply voltage, or

the delay period is a randomly selected delay period relative to at least a portion of the other flash memory devices receiving the power supply voltage; and

after waiting for the delay period, executing a second portion of the instructions for the flash memory device.

10. The tangible processor-readable medium of claim 9 , wherein the flash memory device is part of a column having an associated integer column number, wherein the tangible processor-readable medium enables further actions upon execution by one or more processors, comprising determining the associated column number of the flash memory device, wherein the action of waiting the delay period is accomplished by providing the delay period such that the delay period is determined by multiplying a delay value by the associated column number.

Assignments (8)