Semiconductor device with STI and method for manufacturing the semiconductor device

1. A method for manufacturing a semiconductor device comprising steps of:

(a) forming a mask insulating film pattern on a semiconductor substrate having a memory area and a logic circuit area, said mask insulating film pattern having an opening of an isolation region shape for defining a plurality of active regions;

(b) by using said mask insulating film pattern as an etching mask, etching said semiconductor substrate to form an isolation trench for defining said plurality of active regions;

(c) depositing an isolation material film burying said isolation trench;

(d) subjecting said isolation material film to chemical mechanical polishing to form an isolation region and expose said mask insulating film pattern;

(e) after said step (d), forming a resist pattern covering said logic circuit area, etching said isolation region in said memory area to remove a partial thickness of said isolation region in said memory area;

(f) after said step (e), removing said mask insulating film pattern;

(g) after said step (f), forming a first structure having a first height and extending on an area from the active region in said memory area to a nearby isolation region;

(h) after said step (f), forming a second structure having a second height lower than the first height and extending on an area from the active region in said logic circuit area to a nearby isolation region,

(i) before said step (g), forming a gate insulating film for a memory cell in said plurality of active regions;

(j) removing the gate insulating film for the memory cell in said logic circuit area;

(k) forming a gate insulating film for a MOS transistor in said plurality of active regions in said logic circuit area, and

(l) by using the resist pattern used in said step (e), implanting ions for threshold voltage control in said memory area.

2. A method for manufacturing a semiconductor device comprising steps of:

(a) forming a mask insulating film pattern on a semiconductor substrate having a memory area and a logic circuit area, said mask insulating film pattern having an opening of an isolation region shape for defining a plurality of active regions;

(b) by using said mask insulating film pattern as an etching mask, etching said semiconductor substrate to form an isolation trench for defining said plurality of active regions;

(c) depositing an isolation material film burying said isolation trench;

(d) subjecting said isolation material film to chemical mechanical polishing to form an isolation region and expose said mask insulating film pattern;

(e) after said step (d), forming a resist pattern covering said logic circuit area, etching said isolation region in said memory area to remove a partial thickness of said isolation region in said memory area;

(f) after said step (e), removing said mask insulating film pattern;

(g) after said step (f), forming a first structure having a first height and extending on an area from the active region in said memory area to a nearby isolation region;

(h) after said step (f), forming a second structure having a second height lower than the first height and extending on an area from the active region in said logic circuit area to a nearby isolation region,

(i) before said step (g), forming a gate insulating film for a memory cell in said plurality of active regions;

(j) removing the gate insulating film for the memory cell in said logic circuit area; and

(k) forming a gate insulating film for a MOS transistor in said plurality of active regions in said logic circuit area;

wherein said step (g) comprises steps of:

(g-1) forming a floating gate layer covering said gate insulating film for the memory cell;

(g-2) patterning said floating gate layer along a gate width direction;

(g-3) forming an inter-gate insulating film on said semiconductor substrate, said inter-gate insulating film covering said floating gate layer patterned along the gate width direction;

(g-4) patterning said inter-gate insulating film;

(g-5) forming a gate electrode layer on said substrate, said gate electrode layer covering said patterned inter-gate insulating film; and

(g-6) patterning said gate electrode layer and further patterning said inter-gate insulating film and said floating gate layer along a gate length direction.

3. The method for manufacturing a semiconductor device according to claim 2 , wherein said step (h) comprises steps of:

(h-1) together with said step (g-5), forming a gate electrode layer on said gate insulating film for the MOS transistor in said logic circuit area; and

(h-2) patterning said gate electrode layer in said logic circuit area.

4. The method for manufacturing a semiconductor device according to claim 2 , wherein said step (e) forms a step in said isolation region, and said step (g-2) leaves a dummy floating gate on said step in said isolation region.

5. The method for manufacturing a semiconductor device according to claim 4 , wherein said step (g-4) leaves a dummy inter-gate insulating film on a partial surface of said dummy floating gate, and said step (g-6) leaves a dummy gate on said dummy floating gate and said dummy inter-gate insulating film.

6. A method for manufacturing a semiconductor device comprising steps of:

(a) forming an isolation trench in a semiconductor substrate having first and second areas, said isolation trench defining first active region and second active region in said first area and second area, respectively, while a first insulating film pattern and a second insulating film pattern covering said first active region and said second active region, respectively;

(c) depositing an isolation material film burying said isolation trench to form a first isolation region and a second isolation region located in said first area and said second area, respectively;

(d) removing part of said isolation material film to expose said first insulating film pattern and said second insulating film pattern;

(e) after said step (d), etching part of said first isolation region to remove a partial thickness of said first isolation region in said first area and to keep a thickness of said second isolation region;

(f) after said step (e), removing said first insulating film pattern and said second insulating film pattern;

(g) after said step (f), forming a first structure having a first height and extending on an area from the first active region to said first isolation region; and

(h) after said step (f), forming a second structure having a second height lower than the first height and extending on an area from the second active region to said second isolation region which has a surface higher than a surface of said first isolation region and higher than a surface of said second active region,

wherein:

said first area is a memory area and said second area is a logic circuit area; and

the manufacture method further comprises steps of:

(i) before said step (g), forming a first gate insulating film in said first active region and said second active region;

(j) removing the first gate insulating film in said second area; and

(k) forming a second gate insulating film in said second active region, further comprising a step of:

(l) by using the resist pattern used in said step (e), implanting ions for threshold voltage control in said memory area.

7. A method for manufacturing a semiconductor device comprising steps of:

(a) forming an isolation trench in a semiconductor substrate having first and second areas, said isolation trench defining first active region and second active region in said first area and second area, respectively, while a first insulating film pattern and a second insulating film pattern covering said first active region and said second active region, respectively;

(c) depositing an isolation material film burying said isolation trench to form a first isolation region and a second isolation region located in said first area and said second area, respectively;

(d) removing part of said isolation material film to expose said first insulating film pattern and said second insulating film pattern;

(e) after said step (d), etching part of said first isolation region to remove a partial thickness of said first isolation region in said first area and to keep a thickness of said second isolation region;

(f) after said step (e), removing said first insulating film pattern and said second insulating film pattern;

(g) after said step (f), forming a first structure having a first height and extending on an area from the first active region to said first isolation region; and

(h) after said step (f), forming a second structure having a second height lower than the first height and extending on an area from the second active region to said second isolation region which has a surface higher than a surface of said first isolation region and higher than a surface of said second active region,

wherein:

said first area is a memory area and said second area is a logic circuit area; and

the manufacture method further comprises steps of:

(i) before said step (g), forming a first gate insulating film in said first active region and said second active region;

(j) removing the first gate insulating film in said second area; and

(k) forming a second gate insulating film in said second active region,

wherein said step (g) comprises steps of:

(g-1) forming a floating gate layer covering said gate insulating film for the memory cell;

(g-2) patterning said floating gate layer along a gate width direction;

(g-3) forming an inter-gate insulating film on said semiconductor substrate, said inter-gate insulating film covering said floating gate layer patterned along the gate width direction;

(g-4) patterning said inter-gate insulating film;

(g-5) forming a gate electrode layer on said substrate, said gate electrode layer covering said patterned inter-gate insulating film; and

(g-6) patterning said gate electrode layer and further patterning said inter-gate insulating film and said floating gate layer along a gate length direction.

8. The method for manufacturing a semiconductor device according to claim 7 , wherein said step (h) comprises steps of:

(h-1) together with said step (g-5), forming a gate electrode layer on said gate insulating film in said logic circuit area; and

(h-2) patterning said gate electrode layer in said logic circuit area.

9. The method for manufacturing a semiconductor device according to claim 7 , wherein said step (e) forms a step in a third isolation region, and said step (g-2) leaves a dummy floating gate on said step in said third isolation region.

10. The method for manufacturing a semiconductor device according to claim 9 , wherein said step (g-4) leaves a dummy inter-gate insulating film on a partial surface of said dummy floating gate, and said step (g-6) leaves a dummy gate on said dummy floating gate and said dummy inter-gate insulating film.

11. The method for manufacturing a semiconductor device according to claim 6 , wherein said steps (g) and (h) form conductors having different numbers of layers.

12. The method for manufacturing a semiconductor device according to claim 7 , wherein said steps (g) and (h) form conductors having different numbers of layers.