Reliable packaging and interconnect structures
Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.
1. A method of manufacturing a semiconductor device, comprising:
forming an electrically conductive interconnect structure on a substrate, wherein:
the electrically conductive interconnect structure partially extends within at least one trench in a dielectric region of the substrate; and
the electrically conductive interconnect structure has a top surface and at least one sidewall;
removing a portion of the top surface and a portion of the at least one sidewall of the electrically conductive interconnect structure to create at least one gap between the at least one sidewall of the electrically conductive interconnect structure and at least one wall of the at least one trench; and
covering the top surface and a portion of the at least one sidewall of the electrically conductive interconnect structure with a dissimilar material to at least partially fill the at least one gap, wherein the dissimilar material comprises a nano-metal.
2. The method of claim 1 wherein the dissimilar material comprises a coupling layer.
3. The method of claim 1 wherein the dissimilar material comprises an adhesion layer.
4. The method of claim 1 wherein the dissimilar material comprises a conducting isolation layer.
5. The method of claim 1 wherein the dissimilar material comprises a barrier layer.
6. The method of claim 1 wherein the interconnect structure is a damascene structure.
7. The method of claim 1 wherein the interconnect structure is a dual damascene structure.
8. The method of claim 1 wherein the interconnect structure is a TSV structure.
9. The method of claim 1 wherein the interconnect structure comprises copper.
10. The method of claim 1 wherein the dissimilar material comprises CoP.
11. The method of claim 1 wherein the dissimilar material comprises NiP.
12. The method of claim 1 wherein the dissimilar material comprises NiW.
13. The method of claim 1 wherein the covering step comprises covering the top surface and a portion of the at least one sidewall of the interconnect structure with a dissimilar material having a thickness of between 2 to 500 nanometers.
14. The method of claim 1
wherein the covering step comprises covering the top surface and a portion of the at least one sidewall of the interconnect structure with a dissimilar material having a thickness of between 5 to 200 nanometers.
15. The method of claim 1 further comprising coating the dissimilar material with a solderable material.
16. The method of claim 1 wherein the dissimilar material does not etch with the interconnect structure.
17. The method of claim 1 wherein the covering step further comprises covering at least 10% of a plurality sidewalls of the interconnect structure with the dissimilar material.
18. The method of claim 1 wherein the covering step further comprises covering at least 33% of side walls the interconnect structure with the dissimilar material.
19. The method of claim 1 wherein the removing step further comprises:
oxidizing a portion of the interconnect structure; and
removing the oxidized portion of the interconnect structure.
20. The method of claim 1 wherein the removing step comprises removing a portion of a plurality of sidewalls of the interconnect structure along at least 10% of a length of the sidewalls.
21. The method of claim 1 wherein the removing step comprises removing a portion of a plurality of sidewalls of the interconnect structure along at least 33% of a length of the sidewalls.
22. A method of manufacturing a semiconductor device, comprising:
forming an electrically conductive interconnect structure on a substrate, wherein: the electrically conductive interconnect structure partially extends within at least one trench in a dielectric region of the substrate; and
the electrically conductive interconnect structure has a top surface and at least one sidewall; and
removing a portion of the top surface and a portion of the at least one sidewall of the electrically conductive interconnect structure to create at least one gap between the at least one sidewall of the electrically conductive interconnect structure and at least one wall of the at least one trench; and
covering the top surface and a portion of the at least one sidewall of the electrically conductive interconnect structure with a dissimilar material to at least partially fill the at least one gap, the dissimilar material having a grain size between 0.5 to 100 nanometers.
23. The method of claim 22 wherein the dissimilar material comprises a coupling layer.
24. The method of claim 22 wherein the dissimilar material comprises at least one of an adhesion layer, a conducting isolation layer, or a barrier layer.
25. The method of claim 22 wherein the interconnect structure is a damascene structure.
26. The method of claim 22 wherein the interconnect structure is a TSV structure.
27. The method of claim 22 wherein the interconnect structure comprises copper.
28. The method of claim 22 wherein the dissimilar material comprises at least one of CoP, NiP or NiW.
29. The method of claim 22 wherein the covering step comprises covering the top surface and a portion of the at least one sidewall of the interconnect structure with a dissimilar material having a thickness of between 2 to 500 nanometers.
30. The method of claim 22 wherein the covering step comprises covering the top surface and a portion of the at least one sidewall of the interconnect structure with a dissimilar material having a thickness of between 5 to 200 nanometers.
31. The method of claim 22 further comprising coating the dissimilar material with a solderable material.
32. The method of claim 22 wherein the dissimilar material does not etch with the interconnect structure.
33. The method of claim 22 wherein the covering step further comprises covering at least 10% of a plurality sidewalls of the interconnect structure with the dissimilar material.
34. The method of claim 22 wherein the covering step further comprises covering at least 33% of a plurality sidewalls of the interconnect structure with the dissimilar material.
35. The method of claim 22 wherein the removing step further comprises:
oxidizing a portion of the interconnect structure; and
removing the oxidized portion of the interconnect structure.
36. The method of claim 22 wherein the removing step comprises removing a portion of a plurality of sidewalls of the interconnect structure along at least 10% of a length of the sidewalls.
37. The method of claim 22 wherein the removing step comprises removing a portion of a plurality of sidewalls of the interconnect structure along at least 33% of a length of the sidewalls.