IP Library Granted Patent US 9,361,488
Granted Patent B2
US 9,361,488 · App. 13/165,733 · Granted Jun 7, 2016

Single or dual complex subcarrier downconversion

Inventor: Dean Kawaguchi (San Jose, CA)
Assignee: Intelleflex Corporation
G06K7/0008G06K19/0723H04Q2213/13095
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Quick Facts
Patent No.
US 9,361,488
App. No.
13/165,733
Granted
Jun 7, 2016
Kind
B2
Abstract

A method for subcarrier downconversion and data detection according to one embodiment includes determining whether to use an upper sideband frequency section of a complex downconverter output, a lower sideband frequency section of the complex downconverter output, or both sideband frequency sections of the complex downconverter output; and processing the output corresponding to the selected sideband frequency section or sections based on the determination, wherein the processing includes correlation and data detection. Such methodology may also be implemented as a system using logic for performing the various operations. Additional systems and methods are also presented.

Claims (22)

1. A method for subcarrier downconversion and data detection, the method comprising:

determining whether to use an upper sideband frequency section of a complex downconverter output, a lower sideband frequency section of the complex downconverter output, or both sideband frequency sections of the complex downconverter output; and

processing, in a circuit, the output corresponding to the selected sideband frequency section or sections based on the determination, wherein the processing includes correlation and data detection,

wherein the circuit includes correlator blocks corresponding to each of the sideband frequency sections;

wherein the correlator blocks include a series of windowed integrators that are configurable for different lengths;

wherein when the determination is to use outputs of both sideband sections, outputs of correlator blocks of the circuit are combined after magnitude detection and before data slicing; and

wherein outputs of the windowed integrators of each correlator block are added in a first path of the correlator block and subtracted in a second path of the correlator block, and wherein the magnitude detection is performed by complex-to-magnitude modules.

2. The method of claim 1 , wherein a determination to use the output of the upper sideband section or the lower sideband section is made to avoid interference.

3. The method of claim 1 , wherein the determination to use the outputs of both the upper sideband section and the lower sideband section is made to improve the sensitivity.

4. The method of claim 1 , wherein the correlator blocks of the circuit include nondelayed integrators and delayed integrators.

5. The method of claim 1 , wherein each of the windowed integrators is a half symbol integrator correlator, wherein correlator variable delay modules provide a delay into two of the windowed integrators, wherein no delay is introduced into another two of the windowed integrators.

6. A system for subcarrier downconversion and data detection, the system comprising:

logic configured to determine whether to use an upper sideband frequency section of a complex downconverter output, a lower sideband frequency section of the complex downconverter output, or both sideband frequency sections of the complex downconverter output; and

a circuit configured to process the output corresponding to the selected sideband frequency section or sections based on the determination, wherein the processing includes correlation and data detection;

wherein the circuit includes correlator blocks corresponding to each of the sideband frequency sections;

wherein the correlator blocks include a series of windowed integrators that are configurable for different lengths;

wherein the outputs of the correlator blocks are combined after magnitude detection and before data slicing when the determination is to use outputs of both sideband sections; and

wherein outputs of the windowed integrators of each correlator block are added in a first path of the correlator block and subtracted in a second path of the correlator block, and wherein the magnitude detection is performed by complex-to-magnitude modules.

7. The system of claim 6 , wherein each of the windowed integrators is a half symbol integrator correlator, wherein correlator variable delay modules provide a delay into two of the windowed integrators, wherein no delay is introduced into another two of the windowed integrators.

8. The system of claim 6 , wherein the complex-to-magnitude modules include a first complex-to-magnitude module and a second complex-to-magnitude module;

wherein the first complex-to-magnitude module receives a first input representative of an in-phase component of a baseband signal, and a second input representative of a quadrature component of the baseband signal; and

wherein the second complex-to-magnitude module receives a third input representative of the in-phase component of the baseband signal, and a fourth input representative of the quadrature component of the baseband signal.

Assignments (2)
CHANGE OF NAME Recorded Feb 10, 2017
From: INTELLEFLEX CORPORATION
To: ZEST LABS, INC.
Reel/Frame 041678/0799 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: KAWAGUCHI, DEAN
To: INTELLEFLEX CORPORATION
Reel/Frame 026593/0336 →
Continuity (2)
Provisional Application 61360883 · Jul 1, 2010
Related Publication 20120002762A1 · Jan 5, 2012