Intelligent voltage regulator

1. A programmable voltage regulator, comprising:

a processing element coupled to receive programming instructions via a programming interface, the processing element configured to execute the programming instructions to generate a selection signal;

a voltage selector configured to receive the selection signal and to apply the selection signal to select one of a plurality of active analog voltages; and

an output voltage generator configured to apply the selected analog voltage to produce a voltage at an output voltage pin of the programmable voltage regulator.

2. The voltage regulator of claim 1 , further comprising:

the voltage regulator adapted to operate the processing element to access a selection value from a memory and to apply the selection value to select one of multiple preset voltage levels to apply to produce the voltage at the output pin.

3. The voltage regulator of claim 2 , further comprising:

the multiple preset voltage levels selected from nodes of a voltage ladder.

4. The voltage regulator of claim 3 , further comprising:

a regulator to reduce current within the voltage regulator and to set a lower output voltage than the one indicated by the selection value.

5. The voltage regulator of claim 1 , adapted to set a zero voltage at the output pin until a minimum threshold voltage is detected at an input to the voltage regulator.

6. The voltage regulator of claim 1 , adapted to detect undesirable behaviors of an attached load associated with one or more output voltage levels, and in response to the detected load behavior to adjust the output voltage away from the output level associated with the undesirable load behavior.

7. The voltage regulator of claim 1 , adapted to dynamically adjust a glitch rejection interval.

8. A voltage regulator, comprising:

a programming interface via which programming instructions may be applied to a processor of the voltage regulator; and

the voltage regulator adapted to operate the processor according to the programming instructions to select one of multiple active internally-generated analog voltage levels to determine an output voltage level of the voltage regulator.

9. The voltage regulator of claim 8 , further comprising:

the multiple distinct internally-generated voltage levels determined from nodes of a voltage ladder.

10. The voltage regulator of claim 8 , further comprising:

a regulator adapted to reduce current within the voltage regulator and to select a lower output voltage than the one selected by the programming instructions.

11. The voltage regulator of claim 8 , adapted to provide no output voltage in response to the programming instructions until a minimum threshold voltage is detected at an input to the voltage regulator.

12. The voltage regulator of claim 8 , adapted to detect undesirable load behavior around one or more output voltage levels selected by the programming instructions, and in response to the detected behavior to adjust the output voltage away from the output voltage level indicated by the programming instructions.

13. The voltage regulator of claim 8 , adapted to dynamically adjust a glitch rejection interval.

14. The voltage regulator of claim 13 , adapted to dynamically increase the glitch rejection interval in proportion to an amount of expected or detected noise.

15. A voltage regulator, comprising:

a processor coupled to a programming interface;

the voltage regulator adapted to operate the processor to apply a multi-bit selection value received via the programming interface and stored in a memory to select one of multiple predetermined active analog voltage levels to determine a voltage at an output pin of the voltage regulator.

16. The voltage regulator of claim 15 , further comprising:

the multiple predetermined voltage levels determined from nodes of a voltage ladder.

17. The voltage regulator of claim 15 , further comprising:

a regulator to reduce current within the voltage regulator and to select a lower output voltage than the one selected by the selection value.

18. The voltage regulator of claim 15 , adapted to provide zero voltage at the output pin until a minimum threshold voltage is detected at an input to the voltage regulator.

19. The voltage regulator of claim 15 , adapted to detect undesirable behavior of an attached load around one or more output voltage levels selected by the selection value, and in response to the detected behavior to adjust the voltage at the output pin away from the selected output voltage level.

20. The voltage regulator of claim 15 , adapted to dynamically adjust a glitch rejection interval.