Data processing device and data processing arrangement for accelerating buffer synchronization

1. A data processing device comprising:

a memory comprising a plurality of memory regions;

a first data processing component;

a control memory comprising, for each memory region of the plurality of memory regions, an indication whether a data access to the memory region may be carried out by the first data processing component; and

a second data processing component;

wherein the first data processing component comprises

a checking circuit configured to check, for a memory region, whether a data access to the memory region may be carried out by the first data processing component based on the indication for the memory region;

a data access circuit configured to carry out the data access to the memory region if a data access to the memory region may be carried out by the first data processing component; and

a setting circuit configured to reset the indication for the memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of the data access of the first data processing component to the memory region;

wherein the indication that a data access to the memory region may be carried out by the first data processing component is the specification that the data block size of a data block stored in the memory region is bigger than zero.

2. The data processing device of claim 1 , wherein the first data processing component further comprises a memory interface for data exchange with the memory.

3. The data processing device of claim 1 , wherein the first data processing component is configured to carry out data accesses to the memory regions in a predetermined order.

4. The data processing device of claim 1 , wherein the first data processing component comprises an input configured to receive the indication.

5. The data processing device of claim 1 , wherein the second data processing component is a processor running a software process and wherein the setting of the indication for a memory region to indicate that the first data processing component may carry out a data access to the memory region is initiated by the software process.

6. The data processing device of claim 1 , wherein the first data processing component further comprises a data processing circuit and an interface configured to forward data read from the memory in course of the data access to the data processing circuit or to provide data to be written to the memory in course of the data access.

7. The data processing device of claim 1 , wherein the memory regions are buffers allocated in a shared memory.

8. The data processing device of claim 1 , wherein the memory regions are of equal size.

9. The data processing device of claim 1 , being a computer.

10. The data processing device of claim 1 , wherein the indication that no data access to the memory region may be carried out by the first data processing component is the specification that the data block size of a data block stored in the memory region is zero.

11. The data processing device of claim 1 , wherein, for at least one memory region, the control memory stores in addition to the indication at least one parameter value according to which the data access is to be carried out or the data stored in the memory region is to be processed by the first data processing component.

12. The data processing device of claim 11 , wherein the control memory is configured to receive the at least one parameter value from the second data processing component.

13. The data processing device of claim 1 , wherein the second data processing component is configured to set the indication for a memory region to indicate that the first data processing component may carry out a data access to the memory region.

14. A data processing component of a data processing device, the data processing component comprising:

a control memory comprising, for each memory region of a plurality of memory regions, an indication whether a data access to the memory region may be carried out by the data processing component;

a checking circuit configured to check, for a memory region, whether a data access to the memory region may be carried out by the data processing component based on the indication for the memory region;

a data access circuit configured to carry out the data access to the memory region if a data access to the memory region may be exclusively carried out by the data processing component;

a setting circuit configured to reset the indication for a memory region to indicate that a data access to the memory region may not be carried out by the data processing component in response to the completion of the data access of the data processing component to the memory region;

wherein the indication that a data access to the memory region may be carried out by the data processing component is the specification that the data block size of a data block stored in the memory region is bigger than zero.

15. A data processing arrangement comprising:

a first memory comprising a plurality of data objects;

a second memory comprising a plurality of data storage units wherein the number of data storage units is lower than the number of data objects;

a data processing circuit configured to access the plurality of data storage units for state information about the plurality of data objects;

a selecting circuit configured to select a data object from the plurality of data objects according to a predetermined rule;

a storing circuit configured to store state information about the selected data object in a data storage unit of the plurality of data storage units;

wherein the state information is an access right to a data object, and the state information that a data access to a data object may be carried out by the data processing circuit is the specification that the data block size of a data block stored in the data object is bigger than zero.

16. The data processing arrangement of claim 15 , wherein the selecting circuit is configured to select the data object according to an ordering of the data objects.

17. The data processing arrangement of claim 15 , wherein the data object is a memory region of a memory.

18. A data processing device comprising:

a memory comprising a plurality of memory regions;

a first data processing component;

a control memory comprising, for each memory region of the plurality of memory regions, an indication whether a data access to the memory region may be carried out by the first data processing component; and

a second data processing component;

wherein the first data processing component comprises

a checking circuit configured to check, for a memory region, whether a data access to the memory region may be carried out by the first data processing component based on the indication for the memory region;

a data access circuit configured to carry out the data access to the memory region if a data access to the memory region may be carried out by the first data processing component; and

a setting circuit configured to reset the indication for the memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of the data access of the first data processing component to the memory region;

wherein the indication that no data access to the memory region may be carried out by the first data processing component is the specification that the data block size of a data block stored in the memory region is zero.