System and method for multi-dimensional encoding and decoding
A system and method for decoding multi-dimensional encoded data. A set of multi-dimensional encoded data may be received encoding each input bit in a set of input bits by multiple different component codes in multiple different encoding dimensions. The multi-dimensional data may potentially have errors. A map may be used to locate each set of intersection bits that encode the same input bit by multiple unsolved component codes. The unsolved component codes may be decoded using one or a plurality of tested error correction hypotheses that yields a decoding success, where each hypothesis correcting a different set of intersection bits for a different input bit. The successful hypothesis may be applied for correcting the multi-dimensional encoded data.
1. A method for decoding multi-dimensional encoded data, the method comprising:
receiving a set of multi-dimensional encoded data encoding each input bit in a set of input bits by multiple different component codes in multiple different encoding dimensions, the multi-dimensional data potentially having errors;
using a map to locate each set of intersection bits that encode the same input bit by multiple unsolved component codes;
decoding the unsolved component codes using one or a plurality of tested error correction hypotheses that yields a decoding success, each hypothesis correcting a different set of intersection bits for a different input bit.
2. The method of claim 1 , wherein the set of intersection bits that encode the same input bit by multiple unsolved component codes has a relatively high probability of having errors.
3. The method of claim 1 , wherein each hypothesis for correcting a different input bit is used sequentially and independently to decode the multi-dimensional data on-the-fly.
4. The method of claim 1 , wherein a different one of the plurality of hypotheses is decoded in each sequential clock cycle.
5. The method of claim 1 , wherein the map defines the locations of multiple intersection bits in the multiple respective dimensions for each input bit tested by the current hypothesis.
6. The method of claim 1 , wherein the map locating the set of intersection bits for each input bit is generated on-the-fly while processing the input bit.
7. The method of claim 6 , wherein the map is generated on-the-fly for each input bit using multiple (M) processing threads, wherein each thread determines the location of the intersection encoding the input bit in a different dimension.
8. The method of claim 7 comprising executing a number (N) of the processing threads in parallel equal to the number (N) of dimensions to determine the locations of the complete intersection set encoding each input bit in the multiple (N) dimensions in a single clock cycle.
9. The method of claim 1 , wherein decoding is successful when a hypothesis generates multi-dimensional encoded data that has a reduced, optimal or threshold error metric in some or all encoding dimensions.
10. The method of claim 9 , wherein, for each hypothesis, error metrics are computed for component codes in all encoding dimensions in parallel.
11. The method of claim 9 , wherein the error metrics are syndrome values.
12. The method of claim 1 , wherein each input bit is encoded with a different component code and/or in a different arrangement of neighboring bits in each dimension.
13. The method of claim 12 , wherein the component codes are BCH codes.
14. The method of claim 1 , wherein (N)-dimensional encoded data includes a plurality of (N) intersection bits encoding each input bit.
15. A system for decoding multi-dimensional encoded data, the method comprising:
a memory to store a set of multi-dimensional encoded data encoding each input bit in a set of input bits by multiple different component codes in multiple different encoding dimensions; and
a processor to receive the set of multi-dimensional encoded data from the memory with potential errors, to use a map to locate each set of intersection bits that encode the same input bit by multiple unsolved component codes and to decode the unsolved component codes using one or a plurality of tested error correction hypotheses that yields a decoding success, wherein each hypothesis corrects a different set of intersection bits for a different input bit.
16. The system of claim 15 , wherein the set of intersection bits that encode the same input bit by multiple unsolved component codes has a relatively high probability of having errors.
17. The system of claim 15 , wherein the processor uses each hypothesis to correct a different input bit sequentially and independently to decode the multi-dimensional data on-the-fly.
18. The system of claim 15 , wherein the processor decodes a different one of the plurality of hypotheses in each sequential clock cycle.
19. The system of claim 15 , wherein the map defines the locations of multiple intersection bits in the multiple respective dimensions for each input bit tested by the current hypothesis.
20. The system of claim 15 , wherein the processor generates the map locating the set of intersection bits for each input bit on-the-fly while processing the input bit.
21. The system of claim 20 , wherein the processor uses multiple (M) processing threads to generate the map on-the-fly for each input bit, wherein the processor uses each thread to determine the location of the intersection encoding the input bit in a different dimension.
22. The system of claim 21 , wherein the processor executes a number (N) of the processing threads in parallel equal to the number (N) of dimensions to determine the locations of the complete intersection set encoding each input bit in the multiple (N) dimensions in a single clock cycle.
23. The system of claim 15 , wherein the processor decodes successfully when a hypothesis generates multi-dimensional encoded data that has a reduced, optimal or threshold error metric in some or all encoding dimensions.
24. The system of claim 23 , wherein, for each hypothesis, the processor computes error metrics for component codes in all encoding dimensions in parallel.
25. The system of claim 23 , wherein the error metrics are syndrome values.
26. The system of claim 15 , wherein the processor encodes each input bit with a different component code and/or in a different arrangement of neighboring bits in each dimension.
27. The system of claim 26 , wherein the component codes are BCH codes.
28. The system of claim 15 , wherein (N)-dimensional encoded data includes a plurality of (N) intersection bits encoding each input bit.