Oscillator settling time allowance
View Patent ↗Techniques are disclosed relating to oscillator settling time allowance. In one embodiment, an apparatus may include an oscillator and oscillation detection and control circuitry. The oscillation detection and control circuitry may be configured to awaken an oscillator at a predetermined time and detect an edge transition of oscillations. The oscillation detection and control circuitry may further be configured to measure the time from the power-on indication to edge transition detection. In one embodiment, the oscillation detection and control circuitry may be configured to store the measured time and use the measured time instead of the predetermined time for subsequent oscillator awakenings. In some embodiments, the apparatus may further include circuitry configured to compensate for an expected oscillator settling behavior.
1. An apparatus, comprising:
an oscillator configured to awaken from a sleep mode at a predetermined time, wherein the oscillator is further configured to oscillate at an output frequency;
a clock configured to maintain a sleep clock when the oscillator is asleep; and
oscillator detection and control circuitry coupled to the clock and the oscillator, wherein the oscillator detection and control circuitry is configured to:
receive the sleep clock from the clock and provide a power-on indication to the oscillator;
detect an edge transition of an oscillation of the oscillator;
measure a time from the power-on indication to edge transition detection; and
store the measured time;
wherein the measured time is used to awaken the oscillator at a first time, wherein the first time is different than the predetermined time.
2. The apparatus of claim 1 , further comprising a low power oscillator that includes the clock, wherein the measured time is based at least in part on measured low power oscillator cycles.
3. The apparatus of claim 1 , further comprising a module configured to perform digital operations after the oscillator begins oscillating but before the oscillator settles to a predetermined tolerance.
4. The apparatus of claim 1 , further comprising a receiver configured to receive a signal after the oscillator begins oscillating but before the oscillator settles to a predetermined tolerance.
5. The apparatus of claim 1 , wherein the oscillator detection and control circuitry is further configured to skip detecting edge transitions for a sleep-wake cycle of the oscillator based on one or more criteria.
6. The apparatus of claim 1 , further comprising a receiver clock configured to receive digital compensation to compensate for a frequency synthesizer drift.
7. A method, comprising:
awakening an oscillator from a sleep mode at a predetermined time;
detecting an edge transition of the oscillator;
measuring the time from the oscillator awakening to edge transition detection; and
storing the measured time;
wherein the measured time is used to awaken the oscillator at a first time, wherein the first time is different than the predetermined time.
8. The method of claim 7 , further comprising:
returning the oscillator to the sleep mode; and
awakening the oscillator from the sleep mode at the first time.
9. The method of claim 7 , wherein the measuring occurs after each awakening of the oscillator.
10. The method of claim 7 , further comprising activating circuitry before the oscillator has settled within a predetermined tolerance.
11. The method of claim 7 , further comprising applying a digital compensation technique to offset a frequency settling behavior of the oscillator.
12. A non-transitory computer readable medium storing program instructions, wherein the program instructions are computer executable to perform:
awakening an oscillator from a sleep mode at a predetermined time;
detecting an edge transition of the oscillator;
measuring the time from the oscillator awakening to edge transition detection; and
storing the measured time;
wherein the measured time is used to awaken the oscillator at a first time, wherein the first time is different than the predetermined time.
13. The non-transitory computer readable storage medium of claim 12 , wherein the program instructions are further computer executable to perform:
returning the oscillator to the sleep mode; and
awakening the oscillator from the sleep mode at the first time.
14. The non-transitory computer readable storage medium of claim 12 , wherein the program instructions are further computer executable to perform activating circuitry before the oscillator has settled within a predetermined tolerance.
15. The non-transitory computer readable storage medium of claim 12 , wherein the program instructions are further computer executable to perform applying a digital compensation technique to offset a frequency settling behavior of the oscillator.
16. The non-transitory computer readable storage medium of claim 15 , wherein the digital compensation technique includes an exponentially-shaped frequency ramp.
17. An apparatus, comprising:
an oscillator configured to awaken from a sleep mode at a time, wherein the oscillator is further configured to oscillate at an output frequency;
a clock configured to maintain a sleep clock when the oscillator is asleep;
oscillator detection and control circuitry coupled to the clock and the oscillator, wherein the oscillator detection and control circuitry is configured to:
receive the sleep clock from the clock and provide a power-on indication to the oscillator;
detect an edge transition of an oscillation of the oscillator;
measure a time from the power-on indication to edge transition detection; and
store the measured time;
wherein the measured time is used to awaken the oscillator at an updated time.