Method and system for split threshold voltage programmable bitcells
Methods and systems for split threshold voltage programmable bitcells are disclosed and may include selectively programming bitcells in a memory device by applying a high voltage to a gate terminal of the bitcells, where the programming burns a conductive hole in an oxide layer above a higher threshold voltage layer in a memory device. The bitcells may comprise an oxide layer and a doped channel, which may comprise a plurality of different threshold voltage layers. The plurality of different threshold voltage layers may comprise at least one layer with a higher threshold voltage and at least one layer with a lower threshold voltage. The oxide may comprise a gate oxide. The bitcell may comprise an anti-fuse device. The layer with a higher threshold voltage may be separated from an output terminal of the bitcell by the at least one layer with a lower threshold voltage.
1. A method comprising:
in a memory device comprising an array of bitcells, each bitcell in said array of bitcells comprising an oxide layer and a doped channel, said doped channel comprising a plurality of different threshold voltage layers, said plurality of different threshold voltage layers comprising at least one layer having a higher threshold voltage and at least one layer having a lower threshold voltage:
selectively programming one or more bitcells in said array of bitcells by applying a high voltage to a gate terminal of said one or more bitcells in said array of bitcells, wherein said programming burns a conductive hole in said oxide layer above said at least one higher threshold voltage layer.
2. The method according to claim 1 , wherein said oxide comprises a gate oxide.
3. The method according to claim 1 , wherein said each bitcell in said array of bitcells comprises an anti-fuse device.
4. The method according to claim 1 , wherein said at least one layer having a higher threshold voltage is separated from an output terminal of said each bitcell in said array of bitcells by said at least one layer having a lower threshold voltage.
5. The method according to claim 1 , wherein said each bitcell in said array of bitcells comprise a complementary metal-oxide semiconductor (CMOS) device.
6. The method according to claim 1 , wherein said at least one lower threshold voltage layer comprises a high time-dependent dielectric breakdown material.
7. The method according to claim 1 , wherein said at least one lower threshold voltage layer comprises a low time-dependent dielectric breakdown material.
8. The method according to claim 1 , wherein said at least one higher threshold voltage layer comprises a low time-dependent dielectric breakdown material.
9. The method according to claim 1 , wherein said at least one higher threshold voltage layer comprises a high time-dependent dielectric breakdown material.
10. The method according to claim 1 , comprising configuring a gate length of said one or more bitcells in said array of bitcells by said programming.
11. The method according to claim 1 , wherein said each bitcell in said array of bitcells comprises an NMOS device.
12. The method according to claim 1 , wherein said each bitcell in said array of bitcells comprises an PMOS device.
13. A system comprising:
a memory device comprising an array of bitcells, each bitcell in said array of bitcells comprising an oxide layer and a doped channel, said doped channel comprising a plurality of different threshold voltage layers, said plurality of different threshold voltage layers comprising at least one layer having a higher threshold voltage and at least one layer having a lower threshold voltage, said memory device being operable to:
selectively program one or more bitcells in said array of bitcells by applying a high voltage to a gate terminal of said one or more bitcells in said array of bitcells, wherein said programming burns a conductive hole in said oxide layer above said at least one higher threshold voltage layer.
14. The system according to claim 13 , wherein said oxide comprises a gate oxide.
15. The system according to claim 13 , wherein said each bitcell in said array of bitcells comprises an anti-fuse device.
16. The system according to claim 15 , wherein said at least one layer having a higher threshold voltage is separated from an output terminal of said each bitcell in said array of bitcells by said at least one layer having a lower threshold voltage.
17. The system according to claim 13 , wherein said each bitcell in said array of bitcells comprise a complementary metal-oxide semiconductor (CMOS) device.
18. The system according to claim 13 , wherein said at least one lower threshold voltage layer comprises a high time-dependent dielectric breakdown material.
19. The system according to claim 13 , wherein said at least one lower threshold voltage layer comprises a low time-dependent dielectric breakdown material.
20. The system according to claim 13 , wherein said at least one higher threshold voltage layer comprises a low time-dependent dielectric breakdown material.
21. The system according to claim 13 , wherein said at least one higher threshold voltage layer comprises a high time-dependent dielectric breakdown material.
22. The system according to claim 13 , wherein said memory device is operable to configure a gate length of said one or more bitcells in said array of bitcells by said programming.
23. The system according to claim 13 , wherein said each bitcell in said array of bitcells comprises an NMOS device.
24. A method, comprising:
in a memory device comprising an array of bitcells, each bitcell in said array of bitcells comprising an oxide layer and a doped channel, said doped channel comprising a plurality of different threshold voltage layers, said plurality of different threshold voltage layers comprising at least one layer having a higher threshold voltage and at least one layer having a lower threshold voltage:
selectively programming one or more bitcells in said array of bitcells by applying a high voltage to a gate terminal of said one or more bitcells in said array of bitcells, wherein said programming burns a conductive hole in said oxide layer above said at least one higher threshold voltage layer and configures a gate length of said one or more bitcells in said array of bitcells.