Textured gate for high current thin film transistors
View Patent ↗A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.
1. A thin film transistor comprising:
an insulator;
a semiconductor;
a textured gate electrode, wherein the textured gate electrode includes a plurality of dried metal droplets spaced from each other on a plane gate surface in a form of microscopic bump texturing;
a source electrode; and
a drain electrode,
wherein the insulator is sandwiched between the semiconductor and the textured gate electrode.
2. The thin film transistor according to claim 1 wherein the source electrode and the drain electrode are deposited over the semiconductor.
3. The thin film transistor according to claim 1 wherein the semiconductor is deposited over the source electrode and the drain electrode.
4. The thin film transistor according to claim 1 wherein the textured gate electrode includes a surface modified in a manner which increases a current flow of the thin film transistor.
5. The thin film transistor according to claim 1 wherein the metal droplets on the plane gate surface are arranged in at least one of a “polka dot” pattern or a random arrangement.
6. The thin film transistor according to claim 1 wherein the metal droplets are arranged in a varying density over the plane gate surface.
7. The thin film transistor according claim 1 wherein at least a portion of the semiconductor takes on the texturing of the gate electrode.
8. The thin film transistor according to claim 1 wherein at least a portion of the insulator takes on the texturing of the gate electrode.
9. A method for fabricating a textured thin film transistor comprising:
forming a textured gate electrode, wherein the step of forming the textured gate electrode includes assembling the textures in a self-assembly process, and wherein the self-assembly process includes texturing by metal buckling to form corrugations;
forming an insulator layer;
forming semiconductor layer, wherein the semiconductor is deposited over the source electrode and the drain electrode; and
forming a source electrode and drain electrode.
10. The method according to claim 9 wherein the forming of the self-assembled textured gate electrode includes modifying a surface of the textured gate electrode in a manner which increases current flow in the thin film transistor.
11. The method according to claim 9 further including providing overlap between the source electrode and the drain electrode and the textured gate electrode to ensure low contact resistance.
12. The method according to claim 9 wherein the forming of the corrugations includes forming a series of ridges positioned to lie along a channel length of the thin film transistor which extends from source electrode to drain electrode.
13. The method according to claim 9 wherein the forming of the corrugations includes a linear texturing of the gate having flat and high curvature stripes.
14. A method for fabricating a textured thin film transistor comprising:
forming a textured gate electrode, wherein the step of forming the textured gate electrode includes texturing by providing a plurality of metal droplets spaced from each other to a plane gate surface and allowing the metal droplets to dry on the plane gate surface, wherein microscopic bump texturing is achieved;
forming an insulator layer;
forming semiconductor layer; and
forming a source electrode and drain electrode;
wherein the metal droplets on the plane gate surface are arranged in at least one of a “polka dot” pattern or a random arrangement, and wherein the metal droplets are arranged in a varying density over the plane gate surface.
15. The method according to claim 9 wherein the step of forming the insulator layer includes using one of a plurality of insulator deposition techniques to effect a thickness of the insulator layer along the sloped or vertical faces of the textured gate.
16. The method according to claim 9 wherein the insulator applied at thinner thicknesses than an insulator applied to a non-textured gate, enhances gate current for operation in a low voltage operation.
17. The method according to claim 9 , wherein the self-assembly process is performed without a predefined pattern for the textures.