DISPLAY DEVICE
A display device with reduced power consumption has pixels coupled with data lines and arranged in a matrix, a signal controller processing input image signals and outputting output image signals, and a data driver applying data voltages, corresponding to output image signals, to the data lines. When all the input image signals have either a first or second value, the output image signals have the first value. The signal controller generates a polarity signal for determining data voltage polarity, and when all the input image signals have either a first or second value, data voltages corresponding to the input image signals have a polarity equivalent to a polarity of previously applied data voltages. The signal controller generates a control signal for controlling the data driver's clock synchronization circuit, and the control signal halts the clock synchronization circuit when an operating frequency is lower than a predetermined value.
1 . A display device, comprising:
a plurality of pixels arranged in a matrix;
a plurality of data lines coupled with the pixels;
a signal controller processing input image signals and outputting output image signals;
a gray voltage generator generating a plurality of gray voltages; and
a data driver comprising a clock synchronization circuit, the data driver for selecting data voltages from the gray voltages where data voltages correspond to the output image signals from the signal controller, and for applying the data voltages to the data lines,
wherein the signal controller generates a control signal for controlling the clock synchronization circuit, and the control signal halts operation of the clock synchronization circuit when an operating frequency of the data driver is lower than a predetermined value.
2 . The display device of claim 1 , wherein the predetermined value is about 100 MHz.
3 . The display device of claim 2 , wherein the signal controller outputs the control signal after the output image signals.
4 . The display device of claim 3 , wherein the data driver comprises a plurality of integrated circuits, and the integrated circuits are coupled with the signal controller in a point-to-point cascading interface.
5 . The display device of claim 4 , wherein the integrated circuits include a plurality of groups of integrated circuits, and the integrated circuits in a first group of integrated circuits are coupled with each other and are disconnected from the integrated circuits in a second group of integrated circuits.
6 . The display device of claim 1 , wherein the signal controller and the data driver communicate with each other using a current representation scheme.