Semiconductor device and structure

1. A device, comprising:

a first layer and a second layer wherein both said first layer and said second layer are mono-crystalline,

wherein said first layer comprises first transistors,

wherein said second layer comprises second transistors,

wherein at least one of said second transistors substantially overlays one of said first transistors, and

wherein both said first transistors and said second transistors are processed following the same lithography step.

2. A device according to claim 1 , further comprising:

a plurality of memory cell control lines wherein said control lines comprise a portion of said first layer or said second layer.

3. A device according to claim 1 , wherein said first transistors and said second transistors comprise side gates.

4. A device according to claim 1 , wherein said device further comprises a dynamic random access memory (DRAM).

5. A device according to claim 1 , wherein said device further comprises a charge-trap type memory.

6. A device according to claim 1 , wherein said device further comprises a floating-gate type memory.

7. A device according to claim 1 , wherein said device further comprises a resistive-random-access memory (RRAM).

8. A device according to claim 1 , wherein said device further comprises a phase-change type memory.

9. A device, comprising:

a first layer and a second layer wherein both said first layer and said second layer are mono-crystalline,

wherein said first layer comprises first transistors and said second layer comprises second transistors,

wherein said device further comprises first select lines as memory cell control lines,

wherein said first select lines comprise a portion of said first layer,

wherein said device further comprises second select lines as memory cell control lines, and

wherein said second select lines comprise a portion of said second layer.

10. A device according to claim 9 , wherein at least one of said second transistors substantially overlays one of said first transistors, wherein both the at least one of said second transistors and said one of said first transistors are processed following the same lithography step.

11. A device according to claim 9 , wherein said first transistors and said second transistors comprise side gates.

12. A device according to claim 9 , wherein said device further comprises a DRAM type memory.

13. A device according to claim 9 wherein said device further comprises a resistive-RAM type memory.

14. A device according to claim 9 , wherein said device further comprises a floating-gate type memory.

15. A device, comprising:

a first mono-crystalline layer and a second mono-crystalline layer,

wherein said first layer comprises first transistors,

wherein said second layer comprises second transistors,

wherein said first transistors and said second transistors are horizontally oriented transistors, and

wherein said first transistors and said second transistors comprise side gates.

16. A device according to claim 15 , further comprising:

a plurality of memory cell control lines embedded within said first layer and said second layer.

17. A device according to claim 15 , wherein at least one of said second transistors substantially overlays one of said first transistors, and wherein both said second transistors and said one of said first transistors are processed following the same lithography step.

18. A device according to claim 15 , wherein said device further comprises a DRAM type memory.

19. A device according to claim 15 , wherein said device further comprises a resistive-RAM type memory.

20. A device according to claim 15 , wherein said device comprises a floating-gate type memory.

21. A device according to claim 15 wherein said device further comprises a phase-change type memory.

22. A device according to claim 15 , wherein said device further comprises a charge-trap type memory.

23. A device according to claim 15 , wherein said second layer is transferred using an ion-cut layer transfer process.