Mapping address bits to improve spread of banks

1. A method implemented by a device, the method comprising:

receiving, by the device, a request including a first address;

performing, by the device, a boolean logic operation on a high order bit and a low order bit of the first address;

performing, by the device, a swapping operation to swap another high order bit with another low order bit of the first address;

forming, by the device, a second address by:

replacing the low order bit of the first address with a result of the boolean logic operation, and

using the swapped other high order bit and the other low order bit; and

sending, by the device, the request to a memory based on the second address.

2. The method of claim 1 , where, when performing the boolean logic operation, the method further comprises:

performing, by the device, an exclusive OR operation on the high order bit and the low order bit.

3. The method of claim 1 , further comprising:

performing, by the device, another boolean logic operation on another high order bit and another low order bit of the first address; and

forming, by the device, the second address by replacing the low order bit of the first address with the result of the boolean logic operation and the other low order bit of the first address with a result of the other boolean logic operation.

4. The method of claim 3 , where the result of the boolean logic operation is used as the first bit of the second address and the result of the other boolean logic operation is used as the second bit of the second address.

5. The method of claim 3 , where performing the boolean logic operation includes performing a first exclusive OR operation, and where performing the other boolean logic operation includes performing a second exclusive OR operation.

6. The method of claim 3 , where at least one of the high order bit, the low order bit, the other high order bit, or the other low order bit is programmable.

7. The method of claim 1 , where data is stored in the memory as data sets starting at a plurality of predetermined address offsets in an address space of the memory.

8. A device, comprising:

a plurality of requestors issuing requests;

a memory that includes a plurality of memory banks; and

a control block to:

receive a request from at least one of the requestors, the request including a first address,

perform a boolean logic operation on a high order bit and a low order bit of the first address,

perform a swapping operation to swap another high order bit with another low order bit of the first address,

form a second address by:

replacing the low order bit of the first address with a result of the boolean logic operation, and

using the swapped other high order bit and the other low order bit, and

send the request to a memory based on the second address.

9. The device of claim 8 , where, when performing the boolean logic operation, the control block is further to:

perform an exclusive OR operation on the high order bit and the low order bit.

10. The device of claim 8 , where the control block is further to:

perform another boolean logic operation on another high order bit and another low order bit of the first address; and

form the second address by replacing the low order bit of the first address with the result of the boolean logic operation and the other low order bit of the first address with a result of the other boolean logic operation.

11. The device of claim 10 , where the result of the boolean logic operation is used as the first bit of the second address and the result of the other boolean logic operation is used as the second bit of the second address.

12. The device of claim 10 , where, when performing the boolean logic operation, the control block is to perform a first exclusive OR operation, and where, when performing the other boolean logic operation, the control block is to perform a second exclusive OR operation.

13. The device of claim 10 , where at least one of the high order bit, the low order bit, the other high order bit, or the other low order bit is programmable.

14. The device of claim 8 , where data is stored in the memory as data sets starting at a plurality of predetermined address offsets in an address space of the memory.

15. A non-transitory computer-readable medium including instructions, the instructions comprising:

one or more instructions which, when executed by at least one device, cause the at least one device to receive a request, the request including a first address;

one or more instructions which, when executed by the at least one device, cause the at least one device to perform a boolean logic operation on a high order bit and a low order bit of the first address;

one or more instructions to perform a swapping operation to swap another high order bit with another low order bit of the first address;

one or more instructions which, when executed by the at least one device, cause the at least one device to form a second address by:

replacing the low order bit of the first address with a result of the boolean logic operations, and

using the swapped other high order bit and the other low order bit; and

one or more instructions which, when executed by the at least one device, cause the at least one device to send the request to a memory based on the second address.

16. The medium of claim 15 , further comprising:

one or more instructions to perform an exclusive OR operation on the high order bit and the low order bit when performing the boolean logic operation.

17. The medium of claim 15 , further comprising:

one or more instructions to perform another boolean logic operation on another high order bit and another low order bit of the first address; and

one or more instructions to form the second address by replacing the low order bit of the first address with the result of the boolean logic operation and the other low order bit of the first address with a result of the other boolean logic operation.

18. The medium of claim 17 , where the result of the boolean logic operation is used as the first bit of the second address and the result of the other boolean logic operation is used as the second bit of the second address.

19. The medium of claim 17 , where the one or more instructions to perform the boolean logic operation include one or more instructions to perform a first exclusive OR operation, and where the one or more instructions to perform the other boolean logic operation include one or more instructions to perform a second exclusive OR operation.

20. The medium of claim 15 , where data is stored in the memory as data sets starting at a plurality of predetermined address offsets in an address space of the memory.