The described embodiments may provide a chemical detection circuit. The chemical detection circuit may comprise a column of chemically-sensitive pixels. Each chemically-sensitive pixel may comprise a chemically-sensitive transistor, and a row selection device. The chemical detection circuit may further comprise a column interface circuit coupled to the column of chemically-sensitive pixels and an analog-to-digital converter (ADC) coupled to the column interface circuit. Each column interface circuit and column-level ADC may be arrayed with other identical circuits and share critical resources such as biasing and voltage references, thereby saving area and power.
1. A chemical detection circuit, comprising:
a column of chemically-sensitive pixels, each pixel comprising:
a chemically-sensitive transistor; and
a row selection device;
a column interface circuit coupled to the column of chemically-sensitive pixels;
an analog-to-digital converter (ADC) coupled to the column interface circuit, the ADC including an offset cancellation circuit;
an output terminal comprising two pins for low-voltage differential signaling; and
a serializer circuit including
a plurality of shift registers to shift data to bit alignment logic for data alignment,
a pair of ping-pong registers to receive the aligned data and latch each parallel word with timing overlap, and
a first multiplexer to select at least one of the ping-pong registers to output data to an encoder;
a serializer coupled to the output terminal and configured to receive encoded data from the encoder; and
a driver to output data from the serializer to the output terminal, wherein the serializer is configured to transmit data signals by low-voltage differential signaling.
2. The chemical detection circuit of claim 1 , wherein the chemically-sensitive transistor is an ion-sensitive field effect transistor (ISFET).
3. The chemical detection circuit of claim 2 , wherein the row selection device is a non-chemically-sensitive transistor.
4. The chemical detection circuit of claim 3 , wherein the ISFET is selected from a group consisting of a N-Metal-Oxide-Semiconductor (NMOS) and a P-Metal-Oxide-Semiconductor (PMOS).
5. The chemical detection circuit of claim 4 , wherein the row selection device is selected from the group consisting of an NMOS and a PMOS.
6. The chemical detection circuit of claim 2 , wherein the ISFET has a floating gate.
7. The chemical detection circuit of claim 1 , wherein the ADC is shared by multiple columns by multiplexing.
8. A chemical sensor, comprising:
a plurality of columns of chemically-sensitive pixels, each column comprising:
a plurality of chemically-sensitive pixels formed in rows, each chemically-sensitive pixel comprising:
a chemically-sensitive transistor; and
a row selection device;
a column interface circuit coupled to the column of chemically-sensitive pixels;
an analog-to-digital converter (ADC) circuit coupled to the column interface circuit, the ADC circuit including an offset cancellation circuit;
an output terminal comprising two pins for low-voltage differential signaling; and
a serializer circuit including
a plurality of shift registers to shift data to bit alignment logic for data alignment,
a pair of ping-pong registers to receive the aligned data and latch each parallel word with timing overlap, and
a first multiplexer to select at least one of the ping-pong registers to output data to an encoder;
a serializer coupled to the output terminal and configured to receive encoded data from the encoder; and
a driver to output data from the serializer to the output terminal, wherein the serializer is configured to transmit data signals by low-voltage differential signaling.
9. The chemical sensor of claim 8 , wherein the chemically-sensitive transistor is an ion-sensitive field effect transistor (ISFET).
10. The chemical sensor of claim 9 , wherein the row selection device is a non-chemically-sensitive transistor.
11. The chemical sensor of claim 10 , wherein the ISFET is selected from a group consisting of a N-Metal-Oxide-Semiconductor (NMOS) and a P-Metal-Oxide-Semiconductor (PMOS).
12. The chemical sensor of claim 11 , wherein the row selection device is selected from the group consisting of a NMOS and a PMOS.
13. The chemical sensor of claim 9 , wherein the ISFET has a floating gate.
14. The chemical sensor of claim 8 , wherein the ADC circuit comprises a plurality of ADCs that each is shared by multiple columns of chemically-sensitive pixels by multiplexing, and the ADCs share bias reference voltages and signal reference voltages for area and power savings.
15. The chemical sensor of claim 8 , wherein the ADC circuit comprises a plurality of ADCs that each column of chemically-sensitive pixels has a corresponding ADC, and the ADCs share bias reference voltages and signal reference voltages for area and power savings.