Display device and electronic device
View Patent ↗An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.
1. A display device comprising:
a pixel; and
a driver circuit,
wherein the driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
a first terminal of the first transistor is electrically connected to a fourth wiring, and a second terminal of the first transistor is electrically connected to a third wiring;
a first terminal of the second transistor is electrically connected to a sixth wiring, and a second terminal of the second transistor is electrically connected to the third wiring;
a first terminal of the third transistor is electrically connected to a seventh wiring, a second terminal of the third transistor is electrically connected to a gate of the second transistor, and a gate of the third transistor is electrically connected to the seventh wiring;
a first terminal of the fourth transistor is electrically connected to the sixth wiring, a second terminal of the fourth transistor is electrically connected to the gate of the second transistor, and a gate of the fourth transistor is electrically connected to a gate of the first transistor;
a first terminal of the fifth transistor is electrically connected to a fifth wiring, a second terminal of the fifth transistor is electrically connected to the gate of the first transistor, and a gate of the fifth transistor is electrically connected to a first wiring;
a first terminal of the sixth transistor is electrically connected to the sixth wiring, a second terminal of the sixth transistor is electrically connected to the gate of the first transistor, and a gate of the sixth transistor is electrically connected to the gate of the second transistor;
a first terminal of the seventh transistor is electrically connected to the sixth wiring, a second terminal of the seventh transistor is electrically connected to the gate of the first transistor, and a gate of the seventh transistor is electrically connected to a second wiring; and
a first terminal of the eighth transistor is electrically connected to the sixth wiring, a second terminal of the eighth transistor is electrically connected to the gate of the second transistor, and a gate of the eighth transistor is electrically connected to the first wiring,
wherein a value of a ratio W/L of a channel width W to a channel length L of the first transistor is the highest among values of W/L of the first to eighth transistors.
2. The display device according to claim 1 , wherein the value of the ratio W/L of the channel width W to the channel length L of the first transistor is twice to five times higher than the value of W/L of the fifth transistor.
3. The display device according to claim 1 , wherein a channel length L of the third transistor is larger than a channel length L of the fourth transistor.
4. The display device according to claim 1 , wherein a capacitor is provided between the second terminal and the gate of the first transistor.
5. The display device according to claim 1 , wherein the first to eighth transistors are n-channel transistors.
6. The display device according to claim 1 , wherein each of the first to eighth transistors contains an amorphous silicon layer.
7. The display device according to claim 1 , wherein each of the first to eighth transistors contains an amorphous InGaZnO layer.
8. The display device according to claim 1 , wherein the display device is one of a liquid crystal display device and an EL display device.
9. The display device according to claim 1 , wherein the display device is incorporated in one selected from the group consisting of a camera, a computer, an image reproducing device, a goggle-type display, and a game machine.
10. A computer comprising:
a main body including a keyboard and an LED lamp; and
a housing including a display portion, the display portion including a pixel and a driver circuit,
wherein the driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
a first terminal of the first transistor is electrically connected to a fourth wiring, and a second terminal of the first transistor is electrically connected to a third wiring;
a first terminal of the second transistor is electrically connected to a sixth wiring, and a second terminal of the second transistor is electrically connected to the third wiring;
a first terminal of the third transistor is electrically connected to a seventh wiring, a second terminal of the third transistor is electrically connected to a gate of the second transistor, and a gate of the third transistor is electrically connected to the seventh wiring;
a first terminal of the fourth transistor is electrically connected to the sixth wiring, a second terminal of the fourth transistor is electrically connected to the gate of the second transistor, and a gate of the fourth transistor is electrically connected to a gate of the first transistor;
a first terminal of the fifth transistor is electrically connected to a fifth wiring, a second terminal of the fifth transistor is electrically connected to the gate of the first transistor, and a gate of the fifth transistor is electrically connected to a first wiring;
a first terminal of the sixth transistor is electrically connected to the sixth wiring, a second terminal of the sixth transistor is electrically connected to the gate of the first transistor, and a gate of the sixth transistor is electrically connected to the gate of the second transistor;
a first terminal of the seventh transistor is electrically connected to the sixth wiring, a second terminal of the seventh transistor is electrically connected to the gate of the first transistor, and a gate of the seventh transistor is electrically connected to a second wiring; and
a first terminal of the eighth transistor is electrically connected to the sixth wiring, a second terminal of the eighth transistor is electrically connected to the gate of the second transistor, and a gate of the eighth transistor is electrically connected to the first wiring,
wherein a value of a ratio W/L of a channel width W to a channel length L of the first transistor is the highest among values of W/L of the first to eighth transistors.
11. The computer according to claim 10 , wherein the value of the ratio W/L of the channel width W to the channel length L of the first transistor is twice to five times higher than the value of W/L of the fifth transistor.
12. The computer according to claim 10 , wherein a channel length L of the third transistor is larger than a channel length L of the fourth transistor.
13. The computer according to claim 10 , wherein a capacitor is provided between the second terminal and the gate of the first transistor.
14. The computer according to claim 10 , wherein the first to eighth transistors are n-channel transistors.
15. The computer according to claim 10 , wherein each of the first to eighth transistors contains an amorphous silicon layer.
16. The computer according to claim 10 , wherein each of the first to eighth transistors contains an amorphous InGaZnO layer.