IP Library Granted Patent US 8,493,155
Granted Patent B2
US 8,493,155 · App. 13/176,893 · Granted Jul 23, 2013

Multiband voltage controlled oscillator without switched capacitor

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Quick Facts
Patent No.
US 8,493,155
App. No.
13/176,893
Granted
Jul 23, 2013
Kind
B2
Abstract

A controlled oscillator includes, connected in parallel, a capacitor configured to be tuneable based upon a first signal, an inductor, and an active impedance. The active impedance is formed by a pair of cross-coupled transistors connected so as to produce a negative resistive component at the terminals of the active impedance. Circuitry produces a degeneracy tuneable by a second signal in the cross-coupled pair, such that the cross-coupled pair produces a capacitive component tuneable based upon the second signal at the terminals of the active impedance.

Claims (32)

1. A controlled oscillator comprising:

a capacitor configured to be tuneable based upon a first signal;

an inductor coupled in parallel with said capacitor;

an active impedance coupled in parallel with said capacitor and comprising a pair of cross-coupled transistors configured to produce a negative resistive component between terminals of the active impedance, with each transistor comprising first and second conduction terminals and with the first conduction terminal being coupled a respective terminal of said capacitor;

a bias current source common to the pair of cross-coupled transistors;

a pair of MOS transistors coupled between said pair of cross-coupled transistors and said bias current source, with each MOS transistor comprising a gate, a source and a drain, with the gates being controlled by a second signal such that the pair of cross-coupled produces a capacitive component tunable by the second signal between the terminals of the active impedance, with the drains being coupled to the second conduction terminals of said pair of cross-coupled transistors, and with the sources being coupled together and to said bias current source.

2. The controlled oscillator according to claim 1 , wherein each MOS transistor operates in a linear mode.

3. The controlled oscillator according to claim 1 , further comprising an oscillator output taken from couplings between said MOS transistors and said pair of cross-coupled transistors.

4. The controlled oscillator according to claim 1 , wherein the second tuning signal varies by steps.

5. A phase locked loop (PLL) comprising:

a phase-frequency comparator;

a low pass filter coupled downstream of said phase-frequency comparator;

a controlled oscillator coupled downstream of said low pass filter; and

a frequency divider coupled to said controlled oscillator;

said controlled oscillator comprising

a capacitor configured to be tuneable based upon a first signal,

an inductor coupled in parallel with said capacitor,

an active impedance coupled in parallel with said capacitor and comprising a pair of cross-coupled transistors configured to produce a negative resistive component between terminals of the active impedance, with each transistor comprising first and second conduction terminals and with the first conduction terminal being coupled a respective terminal of said capacitor,

a bias current source common to the pair of cross-coupled transistors, and

a pair of MOS transistors coupled between said pair of cross-coupled transistors and said bias current source, with each MOS transistor comprising a gate, a source and a drain, with the gates being controlled by a second signal such that the pair of cross-coupled produces a capacitive component tunable by the second signal between the terminals of the active impedance, with the drains being coupled to the second conduction terminals of said pair of cross-coupled transistors, and with the sources being coupled together and to said bias current source.

6. The PLL according to claim 5 , wherein each MOS transistor operates in a linear mode.

7. The PLL according to claim 5 , further comprising an oscillator output taken from couplings between said MOS transistors and said pair of cross-coupled transistors.

8. The PLL according to claim 5 , wherein the second tuning signal varies by steps.

9. A method of making a controlled oscillator comprising:

configuring a capacitor to be tuneable based upon a first signal;

coupling an inductor in parallel with the capacitor;

coupling an active impedance in parallel with the capacitor, the active impedance comprising a pair of cross-coupled transistors configured to produce a negative resistive component between terminals of the active impedance, with each transistor comprising first and second conduction terminals and with the first conduction terminal being coupled a respective terminal of said capacitor;

providing a bias current; and

coupling a pair of MOS transistors between the pair of cross-coupled transistors and the bias current source, with each MOS transistor comprising a gate, a source and a drain, with the gates being controlled by a second signal such that the pair of cross-coupled produces a capacitive component tunable by the second signal between the terminals of the active impedance, with the drains being coupled to the second conduction terminals of the pair of cross-coupled transistors, and with the sources being coupled together and to the bias current source.

10. The method according to claim 9 , wherein each MOS transistor operates in a linear mode.

11. The method according to claim 9 , further comprising an oscillator output taken from couplings between said MOS transistors and said pair of cross-coupled transistors.

12. The method according to claim 9 , wherein the second tuning signal varies by steps.

Assignments (2)
CHANGE OF NAME Recorded Jul 1, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 068104/0472 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2011
From: RAZAFIMANDIMBY, STEPHANE
To: STMICROELECTRONICS SA
Reel/Frame 026608/0779 →