External memory controller
View Patent ↗A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.
1. A computing machine comprising:
a memory;
a plurality of computational nodes embodied in an integrated circuit and each configured to make requests for memory accesses to the memory, at least two of the computational nodes being heterogeneous from each other;
a network coupled to the memory and the plurality of computational nodes, the network embodied in the integrated circuit; and
a memory controller node coupled to the network and configured to receive requests for memory accesses by the computational nodes to the memory and generate two-dimensional memory addresses from the requests.
2. The computing machine of claim 1 , wherein at least one of the computational nodes is a processor.
3. The computing machine of claim 1 , wherein at least one of the computational nodes is a hardware accelerator.
4. The computing machine of claim 1 further comprising a data address generator that generates sequences of addresses for both reading from and writing to the memory by the computational nodes.
5. The computing machine of claim 4 , wherein the sequences of addresses are selected based on a data address generator mode.
6. The computing machine of claim 5 , wherein the data address generator mode is selected from one of bit reverse addressing, circular addressing, data reordering, data interlacing, data de-interlacing, rectangular block, and rectangular pixel block modes.
7. The computing machine of claim 5 , wherein one of the plurality of computational nodes desiring access to a memory location obtains the address of the memory location from the data address generator.
8. The computing machine of claim 5 , wherein the data address generator is configurable by parameters from a port on the memory controller to generate the sequence of addresses.
9. A computing machine comprising:
a memory;
a plurality of computational nodes embodied in an integrated circuit and each configured to make requests for memory accesses to the memory, at least two of the computational nodes being heterogeneous from each other;
a network coupled to the memory and the plurality of computational nodes, the network embodied in the integrated circuit; and
a memory controller node coupled to the network and configured to receive requests for memory accesses by the computational nodes to the memory and generate bit reversing memory addresses from the requests.
10. The computing machine of claim 9 , wherein at least one of the computational nodes is a processor.
11. The computing machine of claim 9 , wherein at least one of the computational nodes is a hardware accelerator.
12. The computing machine of claim 9 further comprising a data address generator that generates sequences of addresses for both reading from and writing to the memory by the computational nodes.
13. The computing machine of claim 12 , wherein the sequences of addresses are selected based on a data address generator mode.
14. The computing machine of claim 13 , wherein the data address generator mode is selected from one of two-dimensional addressing, circular addressing, data reordering, data interlacing, data de-interlacing, rectangular block, and rectangular pixel block modes.
15. The computing machine of claim 12 , wherein one of the plurality of computational nodes desiring access to a memory location obtains the address of the memory location from the data address generator.
16. The computing machine of claim 12 , wherein the data address generator is configurable by parameters from a port on the memory controller to generate the sequence of addresses.
17. The computing machine of claim 9 , wherein at least one of the computational nodes performs Fast Fourier transforms or other interleaved or “butterfly” computations.