IP Library Granted Patent US 8,399,928
Granted Patent B2
US 8,399,928 · App. 13/179,214 · Granted Mar 19, 2013

Semiconductor device

Inventors: Tomoaki Ikegami (Hyogo, JP); Kazuyuki Nakanishi (Kyoto, JP); Masaki Tamaru (Kyoto, JP)
Assignee: Panasonic Corporation
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Quick Facts
Patent No.
US 8,399,928
App. No.
13/179,214
Granted
Mar 19, 2013
Kind
B2
Abstract

A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Claims (23)

1. A semiconductor device, comprising:

a standard cell having three or more gate patterns extending in a first direction and arranged at an equal pitch along a second direction orthogonal to the first direction; and

a diode cell located next to the standard cell in the first direction, wherein

the gate patterns included in the standard cell terminate near a cell boundary between the standard cell and the diode cell, with respective end portions located at a same position in the first direction and having an equal width in the second direction, and

the diode cell includes:

at least one diffusion layer which functions as a diode; and

a plurality of opposite end portions formed of a gate pattern, which are located near the cell boundary and opposed to the end portions of the gate patterns included in the standard cell.

2. The semiconductor device of claim 1 , wherein

the diode cell includes a plurality of gate patterns extending in the first direction and respectively having the plurality of opposite end portions.

3. The semiconductor device of claim 2 , wherein

the diode cell includes a second gate pattern extending in the second direction and connected to the plurality of gate patterns such that a grid gate pattern is formed in the diode cell.

4. The semiconductor device of claim 2 , wherein

the plurality of gate patterns included in the diode cell are arranged at a pitch equal to the pitch at which the gate patterns included in the standard cell are arranged in the second direction, with the plurality of opposite end portions located at a same position in the first direction and having an equal width in the second direction.

5. The semiconductor device of claim 4 , wherein

the diffusion layers included in the diode cell are arranged between the plurality of gate patterns at an equal pitch in the second direction, and have an equal width in the second direction.

6. The semiconductor device of claim 1 , wherein

the gate pattern included in the diode cell is a dummy pattern.

7. The semiconductor device of claim 2 , wherein

in the diode cell, the diffusion layers are arranged so as to sandwich at least one of the plurality of gate patterns, and the gate pattern sandwiched between the diffusion layers functions as a gate of a transistor.

8. The semiconductor device of claim 1 , wherein

the diode cell has a dummy pattern which forms at least part of the plurality of opposite end portions,

the dummy pattern includes a pattern body extending in the second direction, and two or more protrusions protruding from the pattern body toward the standard cell in the first direction, and

the protrusions form the opposite end portions.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2015
From: PANASONIC CORPORATION
To: SOCIONEXT INC.
Reel/Frame 035294/0942 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2011
From: IKEGAMI, TOMOAKI; NAKANISHI, KAZUYUKI; TAMARU, MASAKI
To: PANASONIC CORPORATION
Reel/Frame 026661/0165 →
Priority Claims (1)
JP 2010-114517 · May 18, 2010 · national
Continuity (2)
Continuation PCTJP2011000927 · Feb 18, 2011
Related Publication 20110284964A1 · Nov 24, 2011