IP Library Granted Patent US 8,395,447
Granted Patent B2
US 8,395,447 · App. 13/179,339 · Granted Mar 12, 2013

Low-noise amplifier

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,395,447
App. No.
13/179,339
Granted
Mar 12, 2013
Kind
B2
Abstract

A low-noise amplifier comprises an input terminal to which a signal is input; a transistor configured to amplify the signal input to the input terminal; an output terminal through which the amplified signal from the transistor is output; a feedback amount regulator circuit configured to regulate an amplitude of the signal output from the transistor as a feedback amount and output a voltage; a bias circuit configured to generate a bias current fed to the transistor; a differential voltage comparator configured to compare the voltage output from the feedback amount regulator circuit to a reference voltage, determine whether or not a level of the signal input to the input terminal is a level at which a gain of the transistor is suppressed, and increase the bias current fed to the transistor when the differential voltage comparator determines that the level of the signal input to the input terminal is the level at which the gain of the transistor is suppressed; a first input bias circuit configured to generate the reference voltage and apply the reference voltage to one input end of the differential voltage comparator; and a second input bias circuit configured to add a bias voltage to the voltage output from the feedback amount regulator circuit and apply the voltage added with the bias voltage to the other input end of the differential voltage comparator.

Claims (23)

1. A low-noise amplifier comprising:

an input terminal to which a signal is input;

a transistor configured to amplify the signal input to the input terminal;

an output terminal through which the amplified signal from the transistor is output;

a feedback amount regulator circuit configured to regulate an amplitude of the amplified signal output from the transistor as a feedback amount and output a voltage;

a bias circuit configured to generate a bias current fed to the transistor;

a differential voltage comparator configured to compare the voltage output from the feedback amount regulator circuit to a reference voltage, determine whether or not a level of the signal input to the input terminal is a level at which a gain of the transistor is suppressed, and increase the bias current fed to the transistor when the differential voltage comparator determines that the level of the signal input to the input terminal is the level at which the gain of the transistor is suppressed;

a first input bias circuit configured to generate the reference voltage and apply the reference voltage to one input end of the differential voltage comparator; and

a second input bias circuit configured to add a bias voltage to the voltage output from the feedback amount regulator circuit and apply the voltage added with the bias voltage to the other input end of the differential voltage comparator,

wherein the first input bias circuit includes a plurality of resistors connected in series between a power supply terminal and a ground, and is configured to apply a divided voltage generated by dividing a power supply voltage of the power supply terminal by the plurality of resistors to the one input end of the differential voltage comparator; and

the second input bias circuit includes a plurality of resistors connected in series between a power supply terminal and a ground, and is configured to add a divided voltage generated by dividing a power supply voltage of the power supply terminal by the plurality of resistors to the voltage output from the feedback amount regulator circuit and apply the voltage added with the divided voltage, to the other input end of the differential voltage comparator.

2. The low-noise amplifier according to claim 1 , wherein the feedback amount regulator circuit has a configuration in which a resistor and a direct current cut capacitor are connected in series.

3. A low-noise amplifier comprising:

an input terminal to which a signal is input;

a transistor configured to amplify the signal input to the input terminal;

an output terminal through which the amplified signal from the transistor is output;

a feedback amount regulator circuit configured to regulate an amplitude of the amplified signal output from the transistor as a feedback amount and output a voltage;

a bias circuit configured to generate a bias current fed to the transistor;

a differential voltage comparator configured to compare the voltage output from the feedback amount regulator circuit to a reference voltage, determine whether or not a level of the signal input to the input terminal is a level at which a gain of the transistor is suppressed, and increase the bias current fed to the transistor when the differential voltage comparator determines that the level of the signal input to the input terminal is the level at which the gain of the transistor is suppressed;

a first input bias circuit configured to generate the reference voltage and apply the reference voltage to one input end of the differential voltage comparator; and

a second input bias circuit configured to add a bias voltage to the voltage output from the feedback amount regulator circuit and apply the voltage added with the bias voltage to the other input end of the differential voltage comparator,

wherein a signal output from the differential voltage comparator is input to the bias circuit via at least one current mirror circuit.

4. The low-noise amplifier according to claim 3 , wherein the feedback amount regulator circuit has a configuration in which a resistor and a direct current cut capacitor are connected in series.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2011
From: NAKAHASHI, YUSUKE; OKAMOTO, NAOKI
To: PANASONIC CORPORATION
Reel/Frame 026856/0146 →