Enhanced permutable switching network with multicasting signals for interconnection fabric

1. An integrated circuit, comprising: a L-level permutable switching network (L-PSN);

wherein the L-PSN comprises an 0-th level of I 0 number of conductors selectively coupling a (L+1)-th level of I L+1 number of conductors through L levels of conductors and (L+1) sets of switches for L≧1:

wherein the L levels of conductors comprises:

i-th level of conductors of I i number of conductors comprising D[i] sets of conductors and I i−1 ≦I i for each i selected from [1:L], wherein (I i /D[i])>1, D[i]>1, and at least one j selected from [1:L] with D[j]>2;

wherein (I[ 0 ]/Π i=[1:L] D[i])>1;

wherein the I[L+1] number of conductors comprises D[L+1] sets of conductors where D[L+1]>2,

wherein each of the D[L+1] sets of conductors comprises Π i=[1:L] D[i] number of conductors;

wherein the (L+1) sets of switches comprise at least Σ i=[1:L+1] (I i−1 ×D[i]) number of switches,

wherein each i-th set of the (L+1) sets of switches comprises at least (I i−1 ×D[i]) number of switches for i=[1:L+1];

wherein the I i−1 number of conductors of the (i−1)-th level of conductors selectively couple to (I i /D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective at least I i−1 number of switches of the i-th set of switches for i=[1:L+1] without requiring traversal of any other conductors;

wherein the Π i=[1:L] D[i] number of conductors in each of the D[L+1] sets of conductors of the (L+1)-th level of conductors are physically connected to a corresponding number of pins of a corresponding module selected from switching networks and logic cells; and

at least one j selected from [1:L+1],

wherein D[j] is at least two,

wherein each conductor of the I j−1 number of conductors of the (j−1)-th level of conductors selectively couples to at least (D[j]+1) number of conductors of the I j number of conductors of the j-th level of conductors through correspondingly at least (D[j]+1) number of switches without requiring traversal of any other conductors,

wherein the (D[j]+1) number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors of the I j number of conductors, and

wherein the I j−1 number of conductors selectively couple to the I j number of conductors through at least (I j−1 ×D[j]+I j ) number of switches without requiring traversal of any other conductors.

2. The integrated circuit of claim 1 , wherein for D S [j]=((I j−1 /I j )×D[j]), D S [j] is at least two and a Q selected from [1:(I j−1 −D S [j]−1)], and wherein each conductor of the I j−1 number of conductors selectively couples to (D[j]+Q) number of conductors selected at least one conductor from each of the D[j] sets of conductors of the I j number of conductors through (D[j]+Q) number of switches without requiring traversal of any other conductors.

3. The integrated circuit of claim 2 , wherein the I j−1 number of conductors selectively couple to the conductors in each set of the D[j] sets of conductors of the I j number of conductors through at least ((I j−1 +(I j /D[j])×Q) number of switches with a total of at least (I j−1 ×D[j]+I j ×Q) number of switches without requiring traversal of any other conductors.

4. A method of manufacturing an integrated circuit, comprising a L-level permutable switching network (L-PSN), the method comprising:

0-th level of I 0 number of conductors selectively coupling a (L+1)-th level of I L+1 number of conductors through L levels of conductors and (L+1) sets of switches for L≧1, wherein the L levels of conductors comprises:

i-th level of conductors of I i number of conductors comprising D[i] sets of conductors and I i−1 ≦I i for each i selected from [1:L], wherein (I i / D[i])>1, D[i]>1, and at least one j selected from [1:L] with D[j]>2;

wherein (I[ 0 ]/Π i=[1:L] D[i])>1;

wherein the I[L+1] number of conductors comprises D[L+1] sets of conductors where D[L+1]>2;

wherein each of the D[L+1] sets of conductors comprises Π i=[1:L] D[i] number of conductors;

wherein the (L+1) sets of switches comprise at least Σ i=[1:L+1] (I i−1 ×D[i]) number of switches,

wherein each i-th set of the (L+1) sets of switches comprises at least (I i−1 ×D[i]) number of switches for i=[1:L+1];

the I i−1 number of conductors of the (i−1)-th level of conductors selectively coupling to (I i /D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective at least I i−1 number of switches of the i-th set of switches for i=[1:L+1] without requiring traversal of any other conductors;

physically connecting the Π i=[1:L] D[i] number of conductors in each of the D[L+1] sets of conductors of the (L+1)-th level of conductors to a corresponding number of pins of a corresponding module selected from switching networks and logic cells; and

at least one j selected from [1:L+1], wherein D[j] is at least two; and

selectively coupling each conductor of the I j−1 number of conductors of the (j−1)-th level of conductors to at least (D[j]+1) number of conductors of the I j number of conductors of the j-th level of conductors through correspondingly at least (D[j]+1) number of switches without requiring traversal of any other conductors, wherein the (D[j]+1) number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors of the I j number of conductors; and

selectively coupling the I j−1 number of conductors to the I j number of conductors through at least (I j−1 ×D[j]+I j ) number of switches without requiring traversal of any other conductors.

5. The method of claim 4 , wherein for D S [j]=((I j−1 /I j )×D[j]), D S [j] is at least two and a Q selected from [1:(I j−1 −D S [j]−1)], and wherein each conductor of the I j−1 number of conductors selectively couples to (D[j]+Q) number of conductors selected at least one conductor from each of the D[j] sets of conductors of the I j number of conductors through (D[j]+Q) number of switches without requiring traversal of any other conductors.

6. The method of claim 5 , further comprising selectively coupling the I j−1 number of conductors to the conductors in each set of the D[j] sets of conductors of the I j number of conductors through at least ((I j−1 +(I j /D[j])×Q) number of switches with a total of at least (I j−1 ×D[j]+I j ×Q) number of switches without requiring traversal of any other conductors.

7. A non-transitory machine readable medium that stores date representing an integrated circuit layout comprising a L-level permutable switching network (L-PSN), that when executed by a machine causes the machine to perform the following comprising:

0-th level of I 0 number of conductors selectively coupling a (L+1)-th level of I L+1 number of conductors through L levels of conductors and (L+1) sets of switches for L≧1, wherein the L levels of conductors comprises:

i-th level of conductors of I i number of conductors comprising D[i] sets of conductors and I i−1 ≦I i for each i selected from [1:L], wherein (I i /D[i])>1, D[i]>1, and at least one j selected from [1:L] with D[j]>2;

wherein (I[ 0 ]/Π i=[1:L] D[i])>1;

wherein the I[L+1] number of conductors comprises D[L+1] sets of conductors where D[L+1]>2;

wherein each of the D[L+1] sets of conductors comprises Π i=[1:L] D[i] number of conductors;

wherein the (L+1) sets of switches comprise at least Σ i=[1:L+1] ×D[i]) number of switches,

wherein each i-th set of the (L+1) sets of switches comprises at least (I i−1 ×D[i]) number of switches for i=[1:L+1];

the I i−1 number of conductors of the (i−1)-th level of conductors selectively coupling to (I i /D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective at least I i−1 number of switches of the i-th set of switches for i=[1:L+1] without requiring traversal of any other conductors;

physically connecting the Π i=[1:L] D[i] number of conductors in each of the D[L+1] sets of conductors of the (L+1)-th level of conductors to a corresponding number of pins of a corresponding module selected from switching networks and logic cells; and

at least one j selected from [1:L+1], wherein D[j] is at least two; and

selectively coupling each conductor of the I j−1 number of conductors of the (j−1)-th level of conductors to at least (D[j]+1) number of conductors of the I j number of conductors of the j-th level of conductors through correspondingly at least (D[j]+1) number of switches without requiring traversal of any other conductors, wherein the (D[j]+1) number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors of the I j number of conductors; and

selectively coupling the I j−1 number of conductors to the I j number of conductors through at least (I j−1 ×D[j]+I j ) number of switches without requiring traversal of any other conductors.

8. The non-transitory machine readable medium of claim 7 , wherein for D S [j]=((I j−1 /I j )×D[j]), D S [j] is at least two and a Q selected from [1:(I j−1 −D S [j]−1)], and wherein each conductor of the I j−1 number of conductors selectively couples to (D[j]+Q) number of conductors selected at least one conductor from each of the D[j] sets of conductors of the I j number of conductors through (D[j]+Q) number of switches without requiring traversal of any other conductors.

9. The non-transitory machine readable medium of claim 8 , wherein the machine is further caused to perform the following comprising selectively coupling the I j−1 number of conductors to the conductors in each set of the D[j] sets of conductors of the I j number of conductors through at least ((I j−1 +(I j /D[j])×Q) number of switches with a total of at least (I j−1 ×D[j]+I j ×Q) number of switches without requiring traversal of any other conductors.