Photon counting UV-APD

1. An avalanche photodiode (APD) comprising:

a first semiconductor substrate having a first doping type;

a first semiconductor layer on top of the first semiconductor substrate, wherein the first semiconductor layer is doped with the first doping type;

a second epitaxial layer on top of the first semiconductor layer, wherein the second epitaxial layer is in-situ doped with the first doping type at a concentration higher than a concentration of the first doping type in the first semiconductor layer;

a third epitaxial layer on top of the second epitaxial layer, wherein the third epitaxial layer is in-situ doped with a second doping type, wherein the doping of the third epitaxial region forms a first p-n junction with the doping of the second epitaxial layer, wherein a carrier multiplication region includes the first p-n junction, and wherein the third epitaxial layer forms an absorption region for photons; and

a first implanted region within the third epitaxial layer, wherein the implanted region is doped with the second doping type.

2. The APD of claim 1 , wherein the first semiconductor layer is a first epitaxial layer and is in-situ doped with the first doping type.

3. The APD of claim 1 , wherein the first semiconductor layer is a second semiconductor substrate that is bonded to the first semiconductor substrate.

4. The APD of claim 1 , wherein the first doping type is n-type and the second doping type is p-type and the semiconductor substrate is made of silicon.

5. The APD of claim 1 further comprising:

a second implanted region of the first doping type overlapping portions of the second epitaxial layer and the third epitaxial layer, the second implanted region forming a second p-n junction with the first implanted region.

6. The APD of claim 3 , wherein the first or second semiconductor substrate has an insulating layer on a surface that is bonded to the second or first semiconductor substrate, respectively.

7. The APD of claim 6 further comprising:

a buried implant region in the second semiconductor substrate, wherein the buried implant region is adjacent the bonded surface of the second semiconductor substrate, wherein the buried implant region is doped with the first doping type.

8. The APD of claim 4 further comprising:

an anode electrode electrically contacting the first implanted region on a top surface of the third epitaxial layer; and

a cathode electrode electrically contacting the semiconductor substrate on the bottom surface of the semiconductor substrate.

9. The APD of claim 8 , wherein the cathode electrode is biased higher than the anode electrode.

10. A process for fabricating an avalanche photodiode, the process comprising:

provisioning a semiconductor wafer having a first doping type;

growing a first epitaxial layer on top of the semiconductor wafer, wherein the first epitaxial layer is in-situ doped with the first doping type;

growing a second epitaxial layer on top of the first epitaxial layer, wherein the second epitaxial layer is in-situ doped with the first doping type at a concentration higher than a concentration of the first doping type in the first epitaxial layer;

growing a third epitaxial layer on top of the second epitaxial layer, wherein the third epitaxial layer is in-situ doped with a second doping type, wherein the third epitaxial layer forms a first p-n junction with the second epitaxial layer, wherein a carrier multiplication region includes the first p-n junction, and wherein the third epitaxial layer forms an absorption region; and

implanting a first region within the third epitaxial layer with ions of the second doping type.

11. The process of claim 10 , wherein an epitaxy chamber grows the first, second, and third epitaxial layers and wherein the first, second, and third epitaxial layers are grown at once in the epitaxy chamber.

12. The process of claim 10 further comprising:

implanting a second region in the second epitaxial layer with ions of the first doping type, wherein the second region is implanted prior to growing the third epitaxial layer and wherein the second region forms a second p-n junction with the first region.

13. The process of claim 10 , wherein the first doping type is n-type and the second doping type is p-type and the semiconductor wafer is made of silicon.

14. The process of claim 13 , further comprising:

forming an anode electrode on top of the third epitaxial layer, wherein the anode electrode electrically contacts the first region:

forming a cathode electrode on bottom of the semiconductor wafer.

15. A process for fabricating an avalanche photodiode, the process comprising:

provisioning a first wafer;

provisioning a second semiconductor wafer having a first doping type;

bonding the first wafer to the second semiconductor wafer;

thinning the second semiconductor wafer;

growing a first epitaxial layer on top of the second semiconductor wafer, wherein the first epitaxial layer is in-situ doped with the first doping type at a concentration higher than a concentration of the first doping type in the second semiconductor wafer;

growing a second epitaxial layer on top of the first epitaxial layer, wherein the second epitaxial layer is in-situ doped with a second doping type, wherein the second epitaxial layer forms a first p-n junction with the first epitaxial layer, wherein a carrier multiplication region includes the first p-n junction, and wherein the second epitaxial layer forms an absorption region; and

implanting a first region within the second epitaxial layer with ions of the second doping type.

16. The process of claim 15 , wherein an epitaxy chamber grows the first and second epitaxial layers and wherein the first and second are grown at once in the epitaxy chamber.

17. The process of claim 15 further comprising:

implanting a second region in the first epitaxial layer with ions of the first doping type, wherein the second region is implanted prior to growing the second epitaxial layer and wherein the second region forms a second p-n junction with the first region.

18. The process of claim 15 , wherein the first doping type is n-type and the second doping type is p-type and the second semiconductor wafer is made of silicon.

19. The process of claim 15 , wherein the first wafer is bonded to the second semiconductor wafer through an insulating layer that, prior to the bonding step, was either part of the first wafer or the second semiconductor wafer.

20. The process of claim 18 , further comprising:

forming an anode electrode on top of the second epitaxial layer, wherein the anode electrode electrically contacts the first region:

forming a cathode electrode on bottom of the first wafer.

21. An array of avalanche photodiodes, the array comprising:

a first semiconductor substrate having a first doping type, a first surface, and a second surface;

a second substrate having a first surface and a second surface, wherein the first surface of the second substrate is bonded with the second surface of the first semiconductor substrate;

an electrically insulating interface at the bond between the first semiconductor substrate and the second substrate, wherein prior to bonding the insulating layer was part of either the first semiconductor substrate or the second substrate;

a plurality of discrete buried implant regions at the second side of the first substrate, the implant regions being of the first doping type;

a plurality of discrete p-n junctions forming a plurality of carrier multiplication regions in the first substrate, wherein each of the p-n junctions vertically overlaps a different implant region of the plurality of discrete buried implant regions and wherein each of the p-n junctions is adjacent an absorption region; and

a plurality of first vias through the second substrate, wherein each of the first vias contact a different implant region of the plurality of discrete buried implant regions.

22. The array of claim 21 , wherein the plurality of first vias contain a metal.

23. The array of claim 21 further comprising:

a plurality of second vias through the second substrate, wherein each of the second vias contact a different implant region of the plurality of discrete buried implant regions and wherein each of the second vias contain a high resistance material thereby acting as a passive quench.

24. The array of claim 21 further, wherein each of the p-n junctions are reversed biased.

25. The array of claim 21 , wherein the first doping type is n-type and the second doping type is p-type and the semiconductor substrate is made of silicon.

26. A process for fabricating an array of avalanche photodiodes, the process comprising:

provisioning a first semiconductor wafer being doped with a first doping type and having a first surface and a second surface opposite the first surface;

implanting ions of a first doping type into the second surface of the first semiconductor wafer to form a plurality of discrete implant regions;

provisioning a second wafer having a first surface and a second surface opposite the first surface;

forming a insulating layer on the second surface of the first semiconductor wafer or the first surface of the second wafer;

bonding the second surface of the first semiconductor wafer to the first surface of the second wafer, wherein the insulating layer is between the first semiconductor wafer and the second wafer;

forming a plurality of discrete p-n junctions to form a plurality of carrier multiplication regions in the first semiconductor wafer, wherein each of the p-n junctions vertically overlaps a different implant region of the plurality of discrete implant regions and wherein each of the p-n junctions is adjacent an absorption region;

etching a plurality of first vias through the second wafer, wherein each of the first vias terminate at a different implant region of the plurality of discrete implant regions;

depositing a fill material in the plurality of first vias.

27. The process of claim 26 , wherein the fill material is a metal.

28. The process of claim 26 further comprising:

etching a plurality of second vias through the second wafer, wherein each of the second vias terminate at a different implant region of the plurality of discrete implant regions.

29. The process of claim 26 , wherein the first doping type is n-type and the second doping type is p-type and the semiconductor wafer is made of silicon.

30. An array of avalanche photodiodes, the array comprising:

a semiconductor substrate having a first doping type;

a plurality of discrete p-n junctions forming a plurality of carrier multiplication regions in the semiconductor substrate, wherein each p-n junction has a top region forming one side of the p-n junction that is located adjacent a top surface of the semiconductor substrate and wherein the top region has doping of a second type;

a plurality of vias through the semiconductor substrate, wherein each of the vias electrically contact a different top region of a different p-n junction of the plurality of discrete p-n junctions and wherein each via is partially lined with an insulating layer; and

an electrode formed on a bottom surface of the semiconductor substrate, wherein the electrode electrically contacts the semiconductors substrate.

31. The array of claim 30 , wherein the p-n junctions are reverse biased.

32. The array of claim 30 , wherein the first doping type is n-type and the second doping type is p-type and the semiconductor substrate is made of silicon.

33. A process for fabricating an array of avalanche photodiodes, the process comprising:

provisioning a semiconductor wafer having a first doping type;

forming a plurality of discrete p-n junctions to form a plurality of carrier multiplication regions in the semiconductor substrate, wherein each p-n junction has a top region forming one side of the p-n junction that is located adjacent a top surface of the semiconductor substrate and wherein the top region has doping of a second type;

etching a plurality of first vias through the a semiconductor wafer, wherein each of the vias electrically contact a different top region of a different p-n junction of the plurality of discrete p-n junctions and wherein each via is partially lined with an insulating layer;

depositing a metal in the plurality of first vias.

34. The process of claim 33 , wherein the first doping type is n-type and the second doping type is p-type and the semiconductor wafer is made of silicon.