Flexible multi-channel amplifiers via wavefront muxing techniques
View Patent ↗This invention aims to present a smart and dynamic power amplifier module that features both power combining and power sharing capabilities. The proposed flexible power amplifier (PA) module consists of a pre-processor, N PAs, and a post-processor. The pre-processor is an M-to-N wavefront (WF) multiplexer (muxer), while the post processor is a N-to-M WF de-multiplexer (demuxer), where N≧M≧2. Multiple independent signals can be concurrently amplified by a proposed multi-channel PA module with a fixed total power output, while individual signal channel outputs feature different power intensities with no signal couplings among the individual signals. In addition to basic configurations, some modules can be configured to feature both functions of parallel power amplifiers and also as M-to-M switches. Other programmable features include configurations of power combining and power redistribution functions with a prescribed amplitude and phase distributions, as well as high power PA with a linearizer.
1. A power amplification (PA) module having an interchangeable-output function, comprising:
a pre-processing unit having a first input, a second input, a first output containing information from said first and second inputs and a second output containing information from said first and second inputs;
a phase-and-amplitude compensation circuit downstream of said pre-processing unit;
a first power amplification unit downstream of said phase-and-amplitude compensation circuit;
a second power amplification unit downstream of said phase-and-amplitude compensation circuit, wherein said first and second power amplification units are arranged in parallel;
a post-processing unit downstream of said first and second power amplification units, wherein said post-processing unit has a third input, a fourth input, a third output containing information from said third and fourth inputs and a fourth output containing information from said third and fourth inputs, wherein said third output is associated with an amplification of said first input, wherein said fourth output is associated with an amplification of said second input, wherein said post-processing unit comprises a first output port for said third output interchangeable with said fourth output and a second output port for said fourth output interchangeable with said third output; and
an optimizer in a signal path between said phase-and-amplitude compensation circuit and said post-processing unit, wherein said optimizer is configured to generate a parameter for said phase-and-amplitude compensation circuit.
2. The power amplification module of claim 1 , wherein said first output comprises a linear combination of said first and second inputs, and said second output comprises a linear combination of said first and second inputs.
3. The power amplification module of claim 1 , wherein said post-processing unit comprises an RF post-processor.
4. The power amplification module of claim 1 , wherein said pre-processing unit comprises a baseband pre-processor.
5. The power amplification module of claim 1 , wherein said first input comprises a baseband digital input.
6. The power amplification module of claim 1 further comprising a first frequency-up converter downstream of said phase-and-amplitude compensation circuit and upstream of said first power amplification unit and a second frequency-up converter downstream of said phase-and-amplitude compensation circuit and upstream of said second power amplification unit, wherein said first and second frequency-up converters are arranged in parallel.
7. The power amplification module of claim 1 , wherein said first power amplification unit has a fifth input in an analog format.
8. The power amplification module of claim 1 further comprising a controller in a signal path between said pre-processing unit and said post-processing unit, wherein said pre-processing unit is configured to be programed based on a parameter altered by said controller.
9. A power amplification (PA) module comprising:
a pre-processing unit having a first input, a second input, a first output containing information from said first and second inputs and a second output containing information from said first and second inputs;
a first power amplification unit downstream of said pre-processing unit;
a second power amplification unit downstream of said pre-processing unit, wherein said first and second power amplification units are arranged in parallel;
a post-processing unit downstream of said first and second power amplification units, wherein said post-processing unit has a third input, a fourth input, a third output containing information from said third and fourth inputs and a fourth output containing information from said third and fourth inputs, wherein said third output is associated with an amplification of said first input, wherein said fourth output is associated with an amplification of said second input; and
a finite-impulse-response (FIR) filter in a signal path between said pre-processing unit and said post-processing unit, wherein said finite-impulse-response (FIR) filter is configured to modulate said first input.
10. The power amplification module of claim 9 further comprising a frequency-down converter in said signal path and between said finite-impulse-response (FIR) filter and said post-processing unit, wherein said frequency-down converter is configured to frequency-down convert said third output.
11. The power amplification module of claim 9 further comprising an A-to-D converter in said signal path and between said finite-impulse-response (FIR) filter and said post-processing unit, wherein said A-to-D converter is configured to output a digitalized signal to said finite-impulse-response (FIR) filter, wherein said finite-impulse-response (FIR) filter is configured to eliminate a frequency band of said digitalized signal.
12. The power amplification module of claim 9 , wherein said finite-impulse-response (FIR) filter is configured to perform an amplitude-and-phase weighting process so as to create a weighting to be injected into said first input.
13. The power amplification module of claim 9 further comprising a first frequency-up converter downstream of said pre-processing unit and upstream of said first power amplification unit and a second frequency-up converter downstream of said pre-processing unit and upstream of said second power amplification unit, wherein said first and second frequency-up converters are arranged in parallel.
14. The power amplification module of claim 9 further comprising a phase-and-amplitude compensation circuit downstream of said pre-processing unit and upstream of said first and second power amplification units, and an optimizer in a signal path between said phase-and-amplitude compensation circuit and said post-processing unit, wherein said optimizer is configured to generate a parameter for said phase-and-amplitude compensation circuit.
15. The power amplification module of claim 9 , wherein said first input comprises a baseband digital input.
16. A power amplification module comprising:
a baseband digital pre-processing unit having a first input, a second input, a first output containing information from said first and second inputs and a second output containing information from said first and second inputs;
a phase-and-amplitude compensation circuit downstream of said baseband digital pre-processing unit;
a first power amplification unit downstream of said phase-and-amplitude compensation circuit;
a second power amplification unit downstream of said phase-and-amplitude compensation circuit, wherein said first and second power amplification units are arranged in parallel;
an RF post-processing unit downstream of said first and second power amplification units, wherein said RF post-processing unit has a third input, a fourth input, a third output containing information from said third and fourth inputs and a fourth output containing information from said third and fourth inputs, wherein said third output is associated with an amplification of said first input, wherein said fourth output is associated with an amplification of said second input; and
an optimizer in a signal path between said phase-and-amplitude compensation circuit and said RF post-processing unit, wherein said optimizer is configured to generate a parameter for said phase-and-amplitude compensation circuit.
17. The power amplification module of claim 16 further comprising a controller in a signal path between said baseband digital pre-processing unit and said RF post-processing unit, wherein said baseband digital pre-processing unit is configured to be programed based on a parameter altered by said controller.
18. The power amplification module of claim 16 , wherein said first power amplification unit has a fifth input in an analog format.
19. The power amplification module of claim 1 further comprising a finite-impulse-response (FIR) filter in a signal path between said pre-processing unit and said post-processing unit, wherein said finite-impulse-response (FIR) filter is configured to modulate said first input.
20. The power amplification module of claim 19 further comprising a frequency-down converter in said signal path and between said finite-impulse-response (FIR) filter and said post-processing unit, wherein said frequency-down converter is configured to frequency-down convert said third output.
21. The power amplification module of claim 19 further comprising an A-to-D converter in said signal path and between said finite-impulse-response (FIR) filter and said post-processing unit, wherein said A-to-D converter is configured to output a digitalized signal to said finite-impulse-response (FIR) filter, wherein said finite-impulse-response (FIR) filter is configured to eliminate a frequency band of said digitalized signal.
22. The power amplification module of claim 19 , wherein said finite-impulse-response (FIR) filter is configured to perform an amplitude-and-phase weighting process so as to create a weighting to be injected into said first input.
23. The power amplification module of claim 19 further comprising a multiplier in said signal path and between said finite-impulse-response (FIR) filter and said pre-processing unit, wherein said multiplier is configured to weigh a signal, output from said finite-impulse-response (FIR) filter, by a coefficient so as to form said second input.