Apparatus and method for calculating an SHA-2 hash function in a general purpose processor

1. A processor comprising:

an execution unit comprising general-purpose hardware processing components and adapted for performing a processor instruction; and

an integrated circuit coupled to the execution unit and adapted primarily for calculating an SHA-2 sigma function in a single processor instruction cycle, the sigma function comprising calculating three different rotate and/or shift state operations and combining results of the calculations in an exclusive-or operation.

2. The processor according to claim 1 , wherein the execution unit comprises a vector processing unit.

3. The processor according to claim 1 , wherein the execution unit supports a 32-bit dataflow, and to calculate a sigma function, the execution unit is adapted to calculate the results for a set of operations of a sigma function and combine the results via an exclusive-or operation.

4. The processor according to claim 3 , wherein the execution unit is further adapted to:

calculate results of each RR2, RR13 and RR22 and combine the results via an exclusive-or operation;

calculate results of each RR6, RR1, and RR25 and combine the results via an exclusive-or operation;

calculate results of each RR7, RR18, and SR3 and combine the results via an exclusive-or operation; and

calculate results of each RR17, RR19, and SR10 and combine the results via an exclusive-or operation.

5. The processor according to claim 4 , wherein the execution unit is adapted to perform the calculations and combinations in parallel.

6. The processor according to claim 1 , wherein the execution unit supports a 64-bit dataflow, and to calculate a sigma function, the execution unit is adapted to calculate the results of a set of operations for a sigma function and combine the results via an exclusive-or operation.

7. The processor according to claim 6 , wherein the execution unit is further adapted to:

calculate results of each RR28, RR34 and RR39 and combine the results via an exclusive-or operation;

calculate results of each RR14, RR18 and RR41 and combine the results via an exclusive-or operation;

calculate results of each RR1, RR8 and SR7 and combine the results via an exclusive-or operation; and

calculate results of each RR19, RR61 and SR6 and combine the results via an exclusive-or operation.

8. The processor according to claim 7 , wherein the execution unit is adapted to perform at least two of the calculations and combinations in parallel.

9. The processor according to claim 7 , wherein the execution unit is adapted to perform at least one calculation and combination within a single processor instruction cycle.

10. The processor according to claim 1 , wherein the processor is adapted to calculate an SHA-2 hash function by using the integrated circuit for calculating an SHA-2 sigma function.

11. The processor according to claim 1 , wherein the processor comprises an out-of-order processor core, and the execution unit is arranged in the out-of-order processor core.

12. A method for calculating an SHA-2 hash function by a processor, the method comprising:

calculating at least one SHA-2 sigma function in a single processor instruction cycle by using an execution unit adapted for performing a processor instruction, the execution unit comprising an integrated circuit primarily designed for calculating the SHA-2 sigma function, the sigma function comprising calculating three different rotate and/or shift state operations and combining results of the calculations in an exclusive-or operation; and

calculating the SHA-2 hash function with general-purpose hardware processing components of the processor based on the sigma function.

13. The method according to claim 12 , wherein the sigma calculation is performed as a vector operation.

14. The method according to claim 12 , wherein for a 32-bit dataflow, the sigma calculation comprises:

calculating results of a set of operations for a sigma function; and

combining the results via an exclusive-or operation.

15. The method according to claim 14 , wherein the sigma calculation further comprises:

calculating results of each RR2, RR13 and RR22 and combining the results via an exclusive-or operation;

calculating results of each RR6, RR1 and RR25 combining the results via an exclusive-or operation;

calculating results of each RR7, RR18 and SR3 and combining the results via an exclusive-or operation; and

calculating results of each RR17, RR19 and SR10 and combining the results via an exclusive-or operation.

16. The method according to claim 15 , wherein the sigma calculations and combinations occur in parallel within a processor cycle.

17. The method according to claim 12 , wherein for a 64-bit dataflow, the sigma calculation comprises:

calculating results of a set operations for a sigma function; and

combining the results via an exclusive-or operation.

18. The method according to claim 17 , wherein the sigma calculation further comprises:

calculating results of each RR28, RR34 and RR39 and combining the results via an exclusive-or operation;

calculating results of each RR14, RR18 and RR41 and combining the results via an exclusive-or operation;

calculating results of each RR1, RR8 and SR7 and combining the results via an exclusive-or operation; and

calculating results of each RR19, RR61 and SR6 and combining the results via an exclusive-or operation.

19. The method according to claim 18 , wherein at least two sets of the sigma calculations and combinations occur in parallel within a processor cycle.

20. A processor comprising:

an execution unit comprising general-purpose hardware processing components and adapted for performing a processor instruction; and

an integrated circuit coupled to the execution unit and adapted exclusively for calculating an SHA-2 sigma function in a single processor instruction cycle, the sigma function comprising calculating three different rotate and/or shift state operations and combining results of the calculations in an exclusive-or operation.