Intelligent power supervisor
View Patent ↗A system can include at least one power supervisor coupled to a power supply voltage and including a processing element configured by instructions stored in a memory to assert at least one output signal in response to at least one comparator output, at least one comparator having a first input coupled to the power supply voltage and a second input coupled to a reference voltage, and configured to provide one comparator output, and at least one programmable voltage divider coupled to one input of the comparator and configured to vary a voltage divided output in response to the processing element.
1. A system, comprising:
at least one power supervisor coupled to a power supply voltage and including a processing element configured by instructions stored in a memory to assert at least one output signal in response to at least one comparator output, at least one comparator having a first input coupled to a programmable threshold voltage and a second input coupled to a reference voltage, and configured to provide the at least one comparator output, and at least one programmable voltage divider coupled to the first input of the comparator and configured to vary a voltage divided output in response to the processing element.
2. The system of claim 1 , wherein:
the memory is configured to store data received on an interface.
3. The system of claim 2 , wherein:
the interface comprises a serial communication interface.
4. The system of claim 1 , wherein:
the memory is a non-volatile memory.
5. The system of claim 1 , further including:
the at least one output signal includes an interrupt signal; and
circuitry, coupled to the power supply voltage, that receives the interrupt signal and is configured to avoid performing predetermined operations in response to the assertion of the interrupt signal.
6. The system of claim 5 , wherein:
the at least one output signal further includes a reset signal; and
the circuitry is further configured to place at least a portion of the circuitry into a reset state in response to the assertion of the reset signal.
7. The system of claim 1 , further including:
the at least one power supervisor is formed in a first integrated circuit (IC); and
the circuitry is formed in a second IC different from the first IC.
8. The system of claim 1 , wherein:
the at least one power supervisor is combined with the circuitry.
9. The system of claim 1 , wherein:
the processing element is further configured to dynamically vary the at least one programmable voltage divider operation in response to a state of the system.
10. A method, comprising:
dynamically asserting at least one output signal with a processing element in response to at least a comparison between a reference voltage and a threshold voltage programmable by the processing element, and a state of a system containing the processing element, wherein the threshold voltage is programmed into a memory by the processing element; and
applying the output signal to circuitry coupled to a power supply voltage.
11. The method of claim 10 , wherein:
the at least one output signal include an interrupt signal.
12. The method of claim 11 , further including:
avoiding predetermined operations by the circuitry in response to the assertion of the interrupt signal by the processing element.
13. The method of claim 11 , further including:
the at least one output signal further includes a reset signal; and
placing at least a portion of the circuitry into a reset mode in response to the assertion of the reset signal by the processing element.
14. The method of claim 10 , further including:
configuring the processing element with instructions stored in a memory.
15. The method of claim 14 , wherein:
the memory comprises a non-volatile memory.
16. A method, comprising:
configuring a processing element with instructions stored in a memory;
setting at least one threshold voltage with a programmable element;
generating a compare result in response to a reference voltage and the at least one threshold voltage; and
controlling an assertion of at least one output signal in response to the compare result with the processing element.
17. The method of claim 16 , wherein:
controlling the assertion of the at least one output signal includes asserting the output signal if the compare result has one value for longer than a delay period.
18. The method of claim 17 , wherein:
the at least one output signal is an interrupt signal.
19. The method of claim 16 , further including:
altering the operation of at least a portion of circuitry coupled to a power supply voltage in response to the assertion of the at least one output signal; and
the processing element and circuitry are combined circuit elements.
20. The method of claim 16 , further including:
altering the operation of at least a portion of circuitry coupled to a power supply voltage in response to the assertion of the at least one output signal; and
the processing element and circuitry are separate circuit elements.