IC with test and shadow access ports and output circuit
The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.
1. An integrated circuit comprising:
A. a TCK lead, a TMS lead, a TDI lead, and a TDO lead;
B. a test access port circuit having a TCK input connected to the TCK lead, a TMS input connected to the TMS lead, a TDI input connected to the TDI lead, a TDO output, a TDO enable output, a data register and an instruction register that are connected to the TDI input and that are selectively coupled to the TDO output, and a state machine that is connected to the TCK input, the TMS input, the data register and the instruction register;
C. a shadow access port circuit having a TCK input connected to the TCK lead, a TMS input connected to the TMS lead, a TDI input connected to the TDI lead, a SDO output, a SDO enable output, a data register and an instruction register that are connected to the TDI input and that are selectively coupled to the TDO output, and a state machine that is connected to the TCK input, the TMS input, the data register and the instruction register; and
D. an output circuit having a TDO input connected to the TDO output, a TDO enable input connected to the TDO enable output, a SDO input connected to the SDO output, a SDO enable input connected to the SDO enable output, and a TDO output connected to the TDO output lead.
2. The integrated circuit of claim 1 in which the state machine of the test access port circuit steps through the states of SELECT-DR, CAPTURE-DR, SHIFT-DR, EXIT 1 -DR, PAUSE-DR, EXIT 2 -DR, and UPDATE-DR.
3. The integrated circuit of claim 2 in which the state machine of the shadow access port circuit steps through the states of SELECT-DR, CAPTURE-DR, SHIFT-DR, and UPDATE-DR without shifting through states of EXIT 1 -DR, PAUSE-DR, or EXIT 2 -DR.
4. The integrated circuit of claim 2 in which the state machines of both access port circuits have a RESET state and an IDLE state.
5. The integrated circuit of claim 1 in which the test access port state machine changes states upon a rising edge of a clock signal on the TCK lead, and the shadow access port state machine changes states upon a falling edge of a clock signal on the TCK lead.