Memory access to a dual in-line memory module form factor flash memory
View Patent ↗Methods, apparatuses, and computer program products for memory access to a dual in-line memory module (DIMM) form factor flash memory are provided. Embodiments include receiving, by a controller from a processor through cacheable memory in the processor, a read request; transmitting, by the controller, the read request to the DIMM form factor flash memory; polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request; copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller; transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller.
1. A method of memory access to a dual in-line memory module (DIMM) form factor flash memory, the method comprising
receiving, by a controller from a processor through cacheable memory in the processor, a read request;
transmitting, by the controller, the read request to the DIMM form factor flash memory;
polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request;
copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller;
transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and
in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller.
2. The method of claim 1 further comprising in response to copying the data to the read queue in the controller, updating, by the controller, in the interface between the controller and the processor, a pointer indicating a position of the data in the read queue in the controller.
3. The method of claim 1 further comprising in response to receiving the invalidate command, invalidating, by the processor, a cached pointer corresponding to a position in the read queue in the controller, the cached pointer stored in the cacheable memory in the processor.
4. The method of claim 1 further comprising:
in response to receiving the invalidate command, reading, by the processor, a pointer from the interface, the pointer indicating a position of the data in the read queue in the controller; and
using, by the processor, the pointer to read the data stored in the read queue in the controller.
5. The method of claim 1 further comprising:
determining, by the processor, whether a cached pointer within the cacheable memory is valid; and
if the cached pointer is valid, reading data in the cacheable memory for a response to the read request.
6. The method of claim 1 wherein the interface includes memory within the controller.
7. The method of claim 1 wherein the read request includes a field indicating a particular processor that generated the read request.
8. An apparatus for memory access to a dual in-line memory module (DIMM) form factor flash memory, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that when executed cause the apparatus to:
receive, by a controller from a processor through cacheable memory in the processor, a read request;
transmit, by the controller, the read request to the DIMM form factor flash memory;
poll, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request;
copy from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller;
transmit, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and
in response to receiving the invalidate command, read by the processor the data stored in the read queue in the controller.
9. The apparatus of claim 8 further comprising computer program instructions to: in response to copying the data to the read queue in the controller, update, by the controller, in the interface between the controller and the processor, a pointer indicating a position of the data in the read queue in the controller.
10. The apparatus of claim 8 further comprising computer program instructions to: in response to receiving the invalidate command, invalidate, by the processor, a cached pointer corresponding to a position in the read queue in the controller, the cached pointer stored in the cacheable memory in the processor.
11. The apparatus of claim 8 further comprising computer program instructions to:
in response to receiving the invalidate command, read, by the processor, a pointer from the interface, the pointer indicating a position of the data in the read queue in the controller; and
use, by the processor, the pointer to read the data stored in the read queue in the controller.
12. The apparatus of claim 8 further comprising computer program instructions to:
determine, by the processor, whether a cached pointer within the cacheable memory is valid; and
if the cached pointer is valid, read data in the cacheable memory for a response to the read request.
13. A computer program product for memory access to a dual in-line memory module (DIMM) form factor flash memory, the computer program product disposed upon a computer readable storage medium, the computer program product comprising computer program instructions capable, when executed, of causing a computer to carry out the steps of:
receiving, by a controller from a processor through cacheable memory in the processor, a read request;
transmitting, by the controller, the read request to the DIMM form factor flash memory;
polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request;
copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller;
transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and
in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller.
14. The computer program product of claim 13 further comprising in response to copying the data to the read queue in the controller, updating, by the controller, in the interface between the controller and the processor, a pointer indicating a position of the data in the read queue in the controller.
15. The computer program product of claim 13 further comprising in response to receiving the invalidate command, invalidating, by the processor, a cached pointer corresponding to a position in the read queue in the controller, the cached pointer stored in the cacheable memory in the processor.
16. The computer program product of claim 13 further comprising:
in response to receiving the invalidate command, reading, by the processor, a pointer from the interface, the pointer indicating a position of the data in the read queue in the controller; and
using, by the processor, the pointer to read the data stored in the read queue in the controller.
17. The computer program product of claim 13 further comprising:
determining, by the processor, whether a cached pointer within the cacheable memory is valid; and
if the cached pointer is valid, reading data in the cacheable memory for a response to the read request.