Solid-state imaging device
View Patent ↗In each photosensitive cell, a photodiode 101 , a transfer gate 102 , a floating diffusion layer section 103 , an amplifier transistor 104 , and a reset transistor 105 are formed in one active region surrounded by a device isolation region. The floating diffusion layer section 103 included in one photosensitive cell is connected not to the amplifier transistor 104 included in that cell but to the gate of the amplifier transistor 104 included in another photosensitive cell adjacent to the one photosensitive cell in the column direction. A polysilicon wire 111 connects the transfer gates 102 arranged in the same row, and a polysilicon wire 112 connects the reset transistors 105 arranged in the same row. For connection in the row direction, only polysilicon wires are used.
1. A solid-state imaging device, comprising;
a plurality of photodiodes configured to perform optical-electrical conversion, the plurality of photodiodes being two-dimensionally arranged in row and column directions on a semiconductor substrate;
a plurality of transfer gates configured to transfer a signal electric charge obtained from performing the optical-electrical conversion, each of the plurality of transfer gates being provided on the semiconductor substrate for a corresponding one of the plurality of photodiodes;
a plurality of floating diffusion layers configured to temporarily store the transferred signal electric charge, each of the plurality of floating diffusion layers being provided for at least one of the plurality of photodiodes and at least one of the corresponding one of the transfer gates;
an amplifier transistor configured to amplify the signal electric charge supplied to a gate of the amplifier transistor; the amplifier transistor being provided on the semiconductor substrate;
a reset transistor configured to reset the signal electric charge stored in one of the plurality of diffusion layers, the reset transistor being provided on the semiconductor substrate;
a vertical signal line configured to output a signal corresponding to the signal electric charge in the plurality of floating diffusion layers;
a signal line connecting one of a plurality of floating diffusion layers with the gate of the amplifier transistor, the signal line including a portion disposed in a column direction;
a first contact configured to receive an output of a source of the amplifier transistor;
a second contact connected to a drain of the reset transistor; and
a third contact connected to a source of the reset transistor, wherein
the gate of the amplifier transistor is connected, in the column direction, to one of the plurality of floating diffusion layers,
the gate of the amplifier transistor and the one of the plurality of floating diffusion layers are formed in different active regions respectively, and
the first, second, and third contacts are aligned in a straight line.