Method for soft modulation in a wireless telecommunication network

1. A method for soft remodulation, in a receiver, of transmissions over a wireless telecommunication system, the method comprising:

obtaining from a Forward Error Correction (FEC) decoder a-posteriori log likelihood ratio (LLR) values in a processor;

converting, in said processor, said a-posteriori LLR values into bit probabilities; and

computing, in said processor, a soft symbol estimate as an expected value of a received half-symbol based on said bit probabilities according to a calculation comprising a number of recursive stages defined by a dimension (q) of said half-symbol, wherein computing said soft symbol estimate includes computing a first stage expected value as E 1 =1−2P 1 , where E 1 comprises said first stage expected value and P 1 comprises a first one of said bit probabilities.

2. The method according to claim 1 , wherein said converting is implemented using a pre-computed Look Up Table (LUT) stored in memory.

3. The method according to claim 1 , wherein said computing is implemented in a Multiplier-Accumulator having a Single Instruction Multiple Data (SIMD) architecture.

4. The method according to claim 1 , wherein said obtaining includes:

receiving estimates of multiple soft symbols in said processor;

converting, with said processor, said multiple soft symbols into multiple a-priori LLR values; and

feeding said LLR values to said FEC decoder to obtain said a posteriori LLR values.

5. The method according to claim 1 , wherein said dimension (q) of said half-symbol is equal to 1, the method further comprising:

outputting said first stage expected value as said expected value of said received half-symbol.

6. The method according to claim 1 , wherein said dimension (q) of said half-symbol is greater than 1, the method further comprising:

calculating said expected value of said half-symbol according to

E k =(2 P k −1)·( E k-1 1−2 q-1 )

as evaluated at k=q, where E k represents a k th stage expected value calculation, and P k represents a k th one of said bit probabilities associated with said half-symbol.

7. The method according to claim 6 , further comprising:

pre-computing values of (2P k −1) as a function of LLR;

storing said pre-computed values in a look-up table (LUT) of a memory; and

accessing said pre-computed values during said computing said soft symbol estimate.

8. A modulator, in a receiver, for soft remodulation of transmissions over a wireless telecommunication system, the modulator comprising:

a processor configured to obtain from a FEC decoder a-posteriori LLR values;

a Look Up Table (LUT) stored in memory, said LUT comprising a plurality of pre-computed bit probabilities associated with said a-posteriori LLR values; and

a soft symbol calculator configured to compute a soft symbol estimate as an expected value of a received half-symbol based on said bit probabilities according to a calculation comprising a number of recursive stages defined by a dimension (q) of said half-symbol, wherein computing said soft symbol estimate includes computing a first stage expected value as E 1 =1−2P 1 , where E 1 comprises said first stage expected value and P 1 comprises a first one of said bit probabilities.

9. The modulator according to claim 8 , wherein said soft symbol calculator is a multiplier-accumulator with Single Instruction Multiple Data (SIMD) architecture.

10. The modulator according to claim 8 , wherein said processor is further configured to:

receive estimates of multiple soft symbols;

convert said multiple soft symbols into multiple a-priori LLR values;

feed said LLR values to said FEC decoder to obtain said a posteriori LLR values.

11. The modulator according to claim 8 , wherein said dimension (q) of said half-symbol is equal to 1, and said soft symbol calculator is further configured to:

output said first stage expected value as said expected value of said received half-symbol.

12. The modulator according to claim 8 , wherein said dimension (q) of said half-symbol is greater than 1, and said soft symbol calculator is further configured to:

calculate said expected value of said half-symbol according to

E k =(2 P k −1)·( E k-1 −2 q-1 )

as evaluated at k=q, where E k represents a k th stage expected value calculation, and P k represents a k th one of said bit probabilities associated with said half-symbol.

13. A computer program product comprising:

a non-transitory computer-readable medium comprising instructions which, when carried out by a processor, cause the processor to:

obtain from a Forward Error Correction (FEC) decoder a-posteriori log likelihood ratio (LLR) values;

convert the a-posteriori LLR values into bit probabilities; and

compute a soft symbol estimate as an expected value of a received half-symbol based on the bit probabilities according to a calculation comprising a number of recursive stages defined by a dimension (q) of said half-symbol, wherein computing said soft symbol estimate includes computing a first stage expected value as E 1 =1−2P 1 , where E 1 comprises said first stage expected value and P 1 comprises a first one of said bit probabilities.

14. The computer program product of claim 13 , wherein said non-transitory computer-readable medium comprises instructions which cause the processor to:

convert the a-posteriori LLR values using a pre-computed Look Up Table (LUT).

15. The computer program product according to claim 13 , wherein said dimension (q) of said half-symbol is equal to 1, and said non-transitory computer-readable medium further comprises instructions causing said processor to:

output said first stage expected value as said expected value of said received half-symbol.

16. The computer program product according to claim 13 , wherein said dimension (q) of said half-symbol is greater than 1, and said non-transitory computer-readable medium further comprises instructions causing said processor to:

calculate said expected value of said half-symbol according to

E k =(2 P k −1)·( E k-1 −2 q-1 )

as evaluated at k=q, where E k represents a k th stage expected value calculation, and P k represents a k th one of said bit probabilities associated with said half-symbol.

17. A receiver apparatus for soft remodulation of transmissions over a wireless telecommunication system, comprising:

means for obtaining from a Forward Error Correction (FEC) decoder a-posteriori log likelihood ratio (LLR) values;

means for converting said a-posteriori LLR values into bit probabilities; and

means for computing a soft symbol estimate as an expected value of a received half symbol based on said bit probabilities according to a calculation comprising a number of recursive stages defined by a dimension (q) of said half-symbol, wherein computing said soft symbol estimate includes computing a first stage expected value as E 1 =1−2P 1 , where E 1 comprises said first stage expected value and P 1 comprises a first one of said bit probabilities.

18. The receiver apparatus of claim 17 , further comprising:

means for receiving estimates of multiple soft symbols;

means for converting said multiple soft symbols into multiple a-priori LLR values; and

means for feeding said LLR values to said FEC decoder to obtain said a posteriori LLR values.

19. The receiver apparatus of claim 17 , wherein said dimension (q) of said half-symbol is equal to 1, and said soft symbol calculator is further configured to:

output said first stage expected value as said expected value of said received half-symbol.

20. The receiver apparatus according to claim 17 , wherein said dimension (q) of said half-symbol is greater than 1, said receiver apparatus further comprising:

means for calculating said expected value of said half-symbol according to

E k =(2 P k −1)·( E k-1 −2 q-1 )

as evaluated at k=q, where E k represents a k th stage expected value calculation, and P k represents a k th one of said bit probabilities associated with said half-symbol.