IP Library Granted Patent US 8,661,279
Granted Patent B2
US 8,661,279 · App. 13/185,799 · Granted Feb 25, 2014

Power capping using C-states

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Quick Facts
Patent No.
US 8,661,279
App. No.
13/185,799
Granted
Feb 25, 2014
Kind
B2
Abstract

An example system includes a power capping controller to assert an output based on exceeding a power threshold for a computer system. A central processing unit (CPU) core is provided to enter a low-power C-state based on the output being asserted via a control path that bypasses an operating system command.

Claims (23)

1. A system comprising:

a power capping controller to assert an output based on exceeding a power threshold for a computer system, and

a central processing unit (CPU) core to enter a low-power C-state based on the output being asserted via a control path that bypasses a software command,

wherein the power capping controller modulates the output by repeatedly asserting and de-asserting the output over a time period such that the amount of time that the CPU operates in the low-power C-state is modulated accordingly.

2. The system of claim 1 , further comprising a power monitor to determine a level of power consumption, the power capping controller asserting the output based on the level of power consumption exceeding the power threshold.

3. The system of claim 1 , wherein the CPU core comprises a plurality of CPU cores, a core of the plurality of CPU cores operating in the low-power C-state based on the output being asserted.

4. The system of claim 3 , further comprising a group of servers, each of the servers comprising a plurality of CPU cores, a server power threshold being assigned to each of the servers in the group of servers to control entering the plurality of CPU cores of each server into a low-power C-state thereof.

5. The system of claim 4 , further comprising a group controller to dynamically allocate power to CPU cores of each of the servers in the group by selectively adjusting the server power threshold for each of the servers.

6. The system of claim 1 , wherein the power capping controller controls a duty cycle of the modulation based on an amount by which the computer system exceeds the power threshold.

7. The system of claim 6 , wherein the power capping controller signals a core to enter the low-power C-state or identifies the low-power C-state to enter based on an external control input of the CPU, the external control input of the CPU receiving a serial control signal or a parallel control signal.

8. The system of claim 1 , wherein the low-power C-state comprises a plurality of low-power C-states, the capping controller asserting the output to select a desired low-power C-state from the plurality of low-power C-states.

9. A processor, comprising:

a central processing unit (CPU) to modulate its operation between a low-power C-state and a normal operating state of an execution unit; and

an external control input associated with the CPU to control the execution unit outside of a software command to modulate the CPU between the low-power C-state and the normal operating state, the external control input being repeatedly asserted and de-asserted over a time period such that the amount of time that the CPU operates in the low-power C-state is modulated accordingly.

10. The processor of claim 9 , wherein the CPU comprises a plurality of CPU cores, each of the plurality of CPU cores modulating its operation between the low-power C-state and the normal operating state based on a command received at the external control input.

11. The processor of claim 10 , the external control input comprises a serial or parallel control to enable or disable the execution unit or to select a desired C-state.

12. A method comprising:

determining, by a computer, system power levels;

comparing, by the computer, system power levels to a power threshold;

asserting, by the computer, an operating system bypass control input to force a processor of the computer into a low power C-state if the power threshold is exceeded such that the system power levels are reduced without operating system intervention; and

modulating, by the computer, the amount of time that the processor operates in the low-power C-state by repeatedly asserting and de-asserting the bypass control input over a time period.

13. The method of claim 12 , further comprising controlling a duty cycle of the modulation based on an amount by which the processor exceeds the power threshold.

14. The method of claim 12 , further comprising selectively controlling multiple cores into or out of the low power C-state via the bypass control input to adjust the system power levels to below the power threshold.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2022
From: OT PATENT ESCROW, LLC
To: VALTRUS INNOVATIONS LIMITED
Reel/Frame 059058/0720 →
PATENT ASSIGNMENT, SECURITY INTEREST, AND LIEN AGREEMENT Recorded Jan 26, 2021
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: OT PATENT ESCROW, LLC
Reel/Frame 055269/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2011
From: GOODRUM, ALAN L.; FAASSE, SCOTT P.; CEPULIS, DARREN J.
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 026614/0358 →